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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-06 01:37:05 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-11 03:55:55 +0000 |
| commit | 934ee74bc0d04b866968f3aba0dc16fe7bccb1d9 (patch) | |
| tree | 7f83d1c12143382a1246c94adb2df310abbb0a5b /ld/ldver.h | |
| parent | 5b576ed1434dfe9d80b7f0a4490c9faca94c0ed0 (diff) | |
| download | gdb-934ee74bc0d04b866968f3aba0dc16fe7bccb1d9.zip gdb-934ee74bc0d04b866968f3aba0dc16fe7bccb1d9.tar.gz gdb-934ee74bc0d04b866968f3aba0dc16fe7bccb1d9.tar.bz2 | |
RISC-V: Fix opcode entries of "vmsge{,u}.vx"
Their check_func should be "match_never", not "match_opcode". The reasons
this error did not cause any disassembler errors are:
1. The problem will not reproduce if "no-aliases" is specified
(because macro instructions are handled as aliases).
2. If not, all affected compressed instructions or their aliases
precede before "vmsge{,u}.vx" macro instructions.
However, it'll easily break if we reorder opcode entries. This commit
fixes this issue before the *accident* occurs.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Make sure that we never match to
vmsge{,u}.vx instructions unless specified in the assembler.
Diffstat (limited to 'ld/ldver.h')
0 files changed, 0 insertions, 0 deletions