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authorKito Cheng <kito.cheng@sifive.com>2019-08-20 17:47:58 +0800
committerKito Cheng <kito.cheng@sifive.com>2019-08-25 19:16:43 -0700
commitdb3b6ecc28a079768dc4661e459c4a68039e8483 (patch)
tree403570cbcf20a4fc6f0c25b53d5fc58b47102a46 /intl
parent23c13d42999cdcf9d224f089891fd3f3c8bdc6aa (diff)
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RISC-V: Improve li expansion for better code density.
li is a pseudo instruction in RISC-V, it might expand to more than one instructions if the immediate value can't fit addi or lui, but the assembler will always using 4-byte instructions during expansion. For example: li a0, 0x12345001 will expand into 12345537 lui a0,0x12345 00150513 addi a0,a0,1 but addi could be compress into 0505 addi a0,a0,1 It because load_const use macro_build to emit instructions, and macro_build call append_insn, and expect it will compress it if possible, but the fact is append_insn never compress anything, So this patch redirect the li expansion flow to normal instruction emission flow via md_assemble, added md_assemblef as an wrapper for that for easier emit instruction with printf-style argument to build instruction. gas/ChangeLog: * tc-riscv.c (md_assemblef): New. (load_const) Use md_assemblef instead of macro_build to emit instructions. * testsuite/gas/riscv/li32.d: New. * testsuite/gas/riscv/li32.s: Ditto. * testsuite/gas/riscv/li64.d: Ditto. * testsuite/gas/riscv/li64.s: Ditto.
Diffstat (limited to 'intl')
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