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authorMaciej W. Rozycki <macro@orcam.me.uk>2021-05-29 03:26:32 +0200
committerMaciej W. Rozycki <macro@orcam.me.uk>2021-05-29 03:26:32 +0200
commitcccc84faff88135ea118250d1b19cfb7aac7e8c1 (patch)
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parentc9de3168a9568c6fb8038b9b83a912a9a391152b (diff)
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MIPS/opcodes: Free up redundant `g' operand code
In the operand handling rewrite made for the MIPS disassembler with commit ab90248154ba ("Add structures to describe MIPS operands"), <https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g' operand code has become redundant for the regular MIPS instruction set by duplicating the OP_REG_COPRO semantics of the `G' operand code. Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI extensions") converted the CTTC1 instruction from the `g' to the `G' operand code, but still left a few instructions behind. Convert the three remaining instructions still using the `g' code then, namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand code, freeing it up for other use. opcodes/ * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", and "mtthc2" to using the `G' rather than `g' operand code for the coprocessor control register referred. include/ * opcode/mips.h: Complement change made to opcodes and remove references to the `g' regular MIPS ISA operand code.
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