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authorAlan Modra <amodra@gmail.com>2002-04-11 10:21:58 +0000
committerAlan Modra <amodra@gmail.com>2002-04-11 10:21:58 +0000
commitcd47f4f16f5148b31cbda56008d65a8554dce33e (patch)
tree9eb63b77d7b1fbb54c523b3a81563e38bd17daed /include/opcode
parent6b8426a663e3099c5cc379e635e01eeabc3b2df6 (diff)
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* i386.h: Add intel mode cmpsd and movsd.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/i386.h6
2 files changed, 10 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index f73a5a8..b8326ff 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2002-04-11 Alan Modra <amodra@bigpond.net.au>
+
+ * i386.h: Add intel mode cmpsd and movsd.
+
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
* mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 43d7208..1527a46 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1232,6 +1232,9 @@ static const template i386_optab[] = {
{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
+/* Intel mode string compare. */
+{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
+{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
@@ -1251,6 +1254,9 @@ static const template i386_optab[] = {
{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
+/* Intel mode string move. */
+{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
+{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"movupd", 2, 0x660f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
{"mulpd", 2, 0x660f59, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },