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| author | Jiawei <jiawei@iscas.ac.cn> | 2024-06-28 00:13:54 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-28 09:57:50 +0800 |
| commit | 805df5e4a8de619aec6d6a808158c302307478e7 (patch) | |
| tree | f07ac486ec954d98cf00dae389cfcea5a9cbfac0 /include/opcode | |
| parent | b3e08eae167e5716a2e005841d4967bf95b05dcf (diff) | |
| download | gdb-805df5e4a8de619aec6d6a808158c302307478e7.zip gdb-805df5e4a8de619aec6d6a808158c302307478e7.tar.gz gdb-805df5e4a8de619aec6d6a808158c302307478e7.tar.bz2 | |
RISC-V: Add Zabha extension CAS instructions.
This patch update the cas instruction in Zabha extension [1],
when both Zabha and Zacas extension enabled.
[1] https://github.com/riscv/riscv-zabha/tags
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension case.
gas/ChangeLog:
* testsuite/gas/riscv/zabha-32.d: New instructions.
* testsuite/gas/riscv/zabha.d: Ditto.
* testsuite/gas/riscv/zabha.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_AMOCAS_B): New opcodes.
(MASK_AMOCAS_B): Ditto.
(MATCH_AMOCAS_H): Ditto.
(MASK_AMOCAS_H): Ditto.
(DECLARE_INSN): New instructions.
* opcode/riscv.h (enum riscv_insn_class): New class case.
opcodes/ChangeLog:
* riscv-opc.c: New instructions.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/riscv-opc.h | 6 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 8763cdf..f0e1d99 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -253,6 +253,8 @@ #define MASK_AMOMAXU_B 0xf800707f #define MATCH_AMOSWAP_B 0x800002f #define MASK_AMOSWAP_B 0xf800707f +#define MATCH_AMOCAS_B 0x2800002f +#define MASK_AMOCAS_B 0xf800707f #define MATCH_AMOADD_H 0x102f #define MASK_AMOADD_H 0xf800707f #define MATCH_AMOXOR_H 0x2000102f @@ -271,6 +273,8 @@ #define MASK_AMOMAXU_H 0xf800707f #define MATCH_AMOSWAP_H 0x800102f #define MASK_AMOSWAP_H 0xf800707f +#define MATCH_AMOCAS_H 0x2800102f +#define MASK_AMOCAS_H 0xf800707f #define MATCH_ECALL 0x73 #define MASK_ECALL 0xffffffff #define MATCH_EBREAK 0x100073 @@ -3728,6 +3732,7 @@ DECLARE_INSN(amomax_b, MATCH_AMOMAX_B, MASK_AMOMAX_B) DECLARE_INSN(amominu_b, MATCH_AMOMINU_B, MASK_AMOMINU_B) DECLARE_INSN(amomaxu_b, MATCH_AMOMAXU_B, MASK_AMOMAXU_B) DECLARE_INSN(amoswap_b, MATCH_AMOSWAP_B, MASK_AMOSWAP_B) +DECLARE_INSN(amocas_b, MATCH_AMOCAS_B, MASK_AMOCAS_B) DECLARE_INSN(amoadd_h, MATCH_AMOADD_H, MASK_AMOADD_H) DECLARE_INSN(amoxor_h, MATCH_AMOXOR_H, MASK_AMOXOR_H) DECLARE_INSN(amoor_h, MATCH_AMOOR_H, MASK_AMOOR_H) @@ -3737,6 +3742,7 @@ DECLARE_INSN(amomax_h, MATCH_AMOMAX_H, MASK_AMOMAX_H) DECLARE_INSN(amominu_h, MATCH_AMOMINU_H, MASK_AMOMINU_H) DECLARE_INSN(amomaxu_h, MATCH_AMOMAXU_H, MASK_AMOMAXU_H) DECLARE_INSN(amoswap_h, MATCH_AMOSWAP_H, MASK_AMOSWAP_H) +DECLARE_INSN(amocas_h, MATCH_AMOCAS_H, MASK_AMOCAS_H) DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) DECLARE_INSN(uret, MATCH_URET, MASK_URET) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index ece2963..fedd478 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -493,6 +493,7 @@ enum riscv_insn_class INSN_CLASS_ZICBOZ, INSN_CLASS_ZABHA, INSN_CLASS_ZACAS, + INSN_CLASS_ZABHA_AND_ZACAS, INSN_CLASS_H, INSN_CLASS_XCVMAC, INSN_CLASS_XCVALU, |