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| author | Chris Demetriou <cgd@google.com> | 2001-10-18 01:42:16 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2001-10-18 01:42:16 +0000 |
| commit | 2228315b47c1647bd28e7d7d0074fd23310080af (patch) | |
| tree | db91d877e14db26b9177119819df7e7ccda29838 /include/opcode | |
| parent | c080b94227d8bb7d994b1ff41d7548019e6a9dc1 (diff) | |
| download | gdb-2228315b47c1647bd28e7d7d0074fd23310080af.zip gdb-2228315b47c1647bd28e7d7d0074fd23310080af.tar.gz gdb-2228315b47c1647bd28e7d7d0074fd23310080af.tar.bz2 | |
[gas/testsuite/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* gas/mips/mips.exp (sb1-ext-ps): New test to test
SB-1 core's paired-single extensions to the MIPS64 ISA.
* gas/mips/sb1-ext-ps.d: New file.
* gas/mips/sb1-ext-ps.s: New file.
[include/opcode/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h (INSN_SB1): New cpu-specific instruction bit.
(OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
if cpu is CPU_SB1.
[opcodes/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_isa_type): Make the ISA used to disassemble
SB-1 binaries include instructions specific to the SB-1.
* mips-opc.c (SB1): New definition.
(mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
"recip.ps", "rsqrt.ps", and "sqrt.ps".
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/mips.h | 5 |
2 files changed, 10 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index ec236b3..cb547e3 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,9 @@ +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h (INSN_SB1): New cpu-specific instruction bit. + (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 + if cpu is CPU_SB1. + 2001-10-17 matthew green <mrg@redhat.com> * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 901c677..b7a0fed 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -328,6 +328,8 @@ struct mips_opcode #define INSN_3900 0x00080000 /* MIPS R10000 instruction. */ #define INSN_10000 0x00100000 +/* Broadcom SB-1 instruction. */ +#define INSN_SB1 0x00200000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -378,7 +380,8 @@ struct mips_opcode && ((insn)->membership & INSN_4100) != 0) \ || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ - && ((insn)->membership & INSN_10000) != 0)) + && ((insn)->membership & INSN_10000) != 0) \ + || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)) /* This is a list of macro expanded instructions. |