aboutsummaryrefslogtreecommitdiff
path: root/include/opcode/tic30.h
diff options
context:
space:
mode:
authorJim Wilson <jim.wilson@linaro.org>2017-04-22 16:36:01 -0700
committerJim Wilson <jim.wilson@linaro.org>2017-04-22 16:36:01 -0700
commitbf1554384b186b448904dbc13ee5374239c88520 (patch)
treea00f30084ee1fc0c491722bcc67b1939e34a0eb4 /include/opcode/tic30.h
parent10f489e57677e670bf980e93896762594e9ad908 (diff)
downloadgdb-bf1554384b186b448904dbc13ee5374239c88520.zip
gdb-bf1554384b186b448904dbc13ee5374239c88520.tar.gz
gdb-bf1554384b186b448904dbc13ee5374239c88520.tar.bz2
Fix ldn/stn multiple instructions. Fix testcases with unaligned data.
sim/aarch64/ * simulator.c (vec_load): Add M argument. Rewrite to iterate over registers based on structure size. (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. (LD1_1): Replace with call to vec_load. (vec_store): Add new M argument. Rewrite to iterate over registers based on structure size. (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. (ST1_1): Replace with call to vec_store. sim/testsuite/sim/aarch64/ * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align data. * sumulh.s: Delete unnecessary data alignment. * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp arguments to match change. * ldn_multiple.s, stn_multiple.s: New.
Diffstat (limited to 'include/opcode/tic30.h')
0 files changed, 0 insertions, 0 deletions