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authorAlan Modra <amodra@gmail.com>2022-05-27 12:37:21 +0930
committerAlan Modra <amodra@gmail.com>2022-05-27 22:08:59 +0930
commit0e3c1eebb22e0ade28b619fb41f42d66ed6fb145 (patch)
tree8a886ac9438d7e9268807c07585eef11a146714d /include/opcode/csky.h
parentaa9b5dbc0f30855aa23034cbd78a1f2025cb9fa9 (diff)
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Remove use of bfd_uint64_t and similar
Requiring C99 means that uses of bfd_uint64_t can be replaced with uint64_t, and similarly for bfd_int64_t, BFD_HOST_U_64_BIT, and BFD_HOST_64_BIT. This patch does that, removes #ifdef BFD_HOST_* and tidies a few places that print 64-bit values.
Diffstat (limited to 'include/opcode/csky.h')
-rw-r--r--include/opcode/csky.h62
1 files changed, 31 insertions, 31 deletions
diff --git a/include/opcode/csky.h b/include/opcode/csky.h
index ed00bfd..faecba1 100644
--- a/include/opcode/csky.h
+++ b/include/opcode/csky.h
@@ -22,46 +22,46 @@
#include "dis-asm.h"
/* The following bitmasks control instruction set architecture. */
-#define CSKYV1_ISA_E1 ((bfd_uint64_t)1 << 0)
-#define CSKYV2_ISA_E1 ((bfd_uint64_t)1 << 1)
-#define CSKYV2_ISA_1E2 ((bfd_uint64_t)1 << 2)
-#define CSKYV2_ISA_2E3 ((bfd_uint64_t)1 << 3)
-#define CSKYV2_ISA_3E7 ((bfd_uint64_t)1 << 4)
-#define CSKYV2_ISA_7E10 ((bfd_uint64_t)1 << 5)
-#define CSKYV2_ISA_3E3R1 ((bfd_uint64_t)1 << 6)
-#define CSKYV2_ISA_3E3R2 ((bfd_uint64_t)1 << 7)
-#define CSKYV2_ISA_10E60 ((bfd_uint64_t)1 << 8)
-#define CSKYV2_ISA_3E3R3 ((bfd_uint64_t)1 << 9)
-
-#define CSKY_ISA_TRUST ((bfd_uint64_t)1 << 11)
-#define CSKY_ISA_CACHE ((bfd_uint64_t)1 << 12)
-#define CSKY_ISA_NVIC ((bfd_uint64_t)1 << 13)
-#define CSKY_ISA_CP ((bfd_uint64_t)1 << 14)
-#define CSKY_ISA_MP ((bfd_uint64_t)1 << 15)
-#define CSKY_ISA_MP_1E2 ((bfd_uint64_t)1 << 16)
-#define CSKY_ISA_JAVA ((bfd_uint64_t)1 << 17)
-#define CSKY_ISA_MAC ((bfd_uint64_t)1 << 18)
-#define CSKY_ISA_MAC_DSP ((bfd_uint64_t)1 << 19)
+#define CSKYV1_ISA_E1 ((uint64_t) 1 << 0)
+#define CSKYV2_ISA_E1 ((uint64_t) 1 << 1)
+#define CSKYV2_ISA_1E2 ((uint64_t) 1 << 2)
+#define CSKYV2_ISA_2E3 ((uint64_t) 1 << 3)
+#define CSKYV2_ISA_3E7 ((uint64_t) 1 << 4)
+#define CSKYV2_ISA_7E10 ((uint64_t) 1 << 5)
+#define CSKYV2_ISA_3E3R1 ((uint64_t) 1 << 6)
+#define CSKYV2_ISA_3E3R2 ((uint64_t) 1 << 7)
+#define CSKYV2_ISA_10E60 ((uint64_t) 1 << 8)
+#define CSKYV2_ISA_3E3R3 ((uint64_t) 1 << 9)
+
+#define CSKY_ISA_TRUST ((uint64_t) 1 << 11)
+#define CSKY_ISA_CACHE ((uint64_t) 1 << 12)
+#define CSKY_ISA_NVIC ((uint64_t) 1 << 13)
+#define CSKY_ISA_CP ((uint64_t) 1 << 14)
+#define CSKY_ISA_MP ((uint64_t) 1 << 15)
+#define CSKY_ISA_MP_1E2 ((uint64_t) 1 << 16)
+#define CSKY_ISA_JAVA ((uint64_t) 1 << 17)
+#define CSKY_ISA_MAC ((uint64_t) 1 << 18)
+#define CSKY_ISA_MAC_DSP ((uint64_t) 1 << 19)
/* Base ISA for csky v1 and v2. */
-#define CSKY_ISA_DSP ((bfd_uint64_t)1 << 20)
-#define CSKY_ISA_DSP_1E2 ((bfd_uint64_t)1 << 21)
-#define CSKY_ISA_DSP_ENHANCE ((bfd_uint64_t)1 << 22)
-#define CSKY_ISA_DSPE60 ((bfd_uint64_t)1 << 23)
+#define CSKY_ISA_DSP ((uint64_t) 1 << 20)
+#define CSKY_ISA_DSP_1E2 ((uint64_t) 1 << 21)
+#define CSKY_ISA_DSP_ENHANCE ((uint64_t) 1 << 22)
+#define CSKY_ISA_DSPE60 ((uint64_t) 1 << 23)
/* Base float instruction (803f & 810f). */
-#define CSKY_ISA_FLOAT_E1 ((bfd_uint64_t)1 << 25)
+#define CSKY_ISA_FLOAT_E1 ((uint64_t) 1 << 25)
/* M_FLOAT support (810f). */
-#define CSKY_ISA_FLOAT_1E2 ((bfd_uint64_t)1 << 26)
+#define CSKY_ISA_FLOAT_1E2 ((uint64_t) 1 << 26)
/* 803 support (803f). */
-#define CSKY_ISA_FLOAT_1E3 ((bfd_uint64_t)1 << 27)
+#define CSKY_ISA_FLOAT_1E3 ((uint64_t) 1 << 27)
/* 807 support (803f & 807f). */
-#define CSKY_ISA_FLOAT_3E4 ((bfd_uint64_t)1 << 28)
+#define CSKY_ISA_FLOAT_3E4 ((uint64_t) 1 << 28)
/* 860 support. */
-#define CSKY_ISA_FLOAT_7E60 ((bfd_uint64_t)1 << 36)
+#define CSKY_ISA_FLOAT_7E60 ((uint64_t) 1 << 36)
/* Vector DSP support. */
-#define CSKY_ISA_VDSP ((bfd_uint64_t)1 << 29)
-#define CSKY_ISA_VDSP_2 ((bfd_uint64_t)1 << 30)
+#define CSKY_ISA_VDSP ((uint64_t) 1 << 29)
+#define CSKY_ISA_VDSP_2 ((uint64_t) 1 << 30)
/* The following bitmasks control cpu architecture for CSKY. */
#define CSKY_ABI_V1 (1 << 28)