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| author | Jose E. Marchesi <jose.marchesi@oracle.com> | 2023-07-21 17:22:58 +0200 |
|---|---|---|
| committer | Jose E. Marchesi <jose.marchesi@oracle.com> | 2023-07-21 20:00:30 +0200 |
| commit | 2f3dbc5fb5e781fc17d8f68f9c960a993f06d801 (patch) | |
| tree | ca0207b2bc57f92ca9a581c4e00faad20f9e7a0e /include/opcode/bpf.h | |
| parent | 01deb24db99ea7909a30679ddb3cd4cba7b14fc7 (diff) | |
| download | gdb-2f3dbc5fb5e781fc17d8f68f9c960a993f06d801.zip gdb-2f3dbc5fb5e781fc17d8f68f9c960a993f06d801.tar.gz gdb-2f3dbc5fb5e781fc17d8f68f9c960a993f06d801.tar.bz2 | |
bpf: opcodes, gas: support for signed register move V4 instructions
This commit adds the signed register move (movs) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
(BPF_OFFSET16_MOVS16): Likewise.
(BPF_OFFSET16_MOVS32): Likewise.
(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R instructions. and MOVS32I instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: Test movs instructions.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu.d: Add expected results.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
Diffstat (limited to 'include/opcode/bpf.h')
| -rw-r--r-- | include/opcode/bpf.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h index f928979..48f06c2 100644 --- a/include/opcode/bpf.h +++ b/include/opcode/bpf.h @@ -131,6 +131,9 @@ typedef uint64_t bpf_insn_word; even if these are multi-byte or infra-byte. Bleh. */ #define BPF_OFFSET16_SDIVMOD ((uint64_t)0x1 << 32) +#define BPF_OFFSET16_MOVS8 ((uint64_t)8 << 32) +#define BPF_OFFSET16_MOVS16 ((uint64_t)16 << 32) +#define BPF_OFFSET16_MOVS32 ((uint64_t)32 << 32) #define BPF_IMM32_END16 ((uint64_t)0x00000010) #define BPF_IMM32_END32 ((uint64_t)0x00000020) @@ -162,6 +165,7 @@ enum bpf_insn_id BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI, BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI, BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI, + BPF_INSN_MOVS8R, BPF_INSN_MOVS16R, BPF_INSN_MOVS32R, BPF_INSN_MOVR, BPF_INSN_MOVI, /* ALU32 instructions. */ BPF_INSN_ADD32R, BPF_INSN_ADD32I, BPF_INSN_SUB32R, BPF_INSN_SUB32I, @@ -171,6 +175,7 @@ enum bpf_insn_id BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I, BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I, BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I, + BPF_INSN_MOVS328R, BPF_INSN_MOVS3216R, BPF_INSN_MOVS3232R, BPF_INSN_MOV32R, BPF_INSN_MOV32I, /* Endianness conversion instructions. */ BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64, |