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| author | Jim Wilson <jimw@sifive.com> | 2018-05-18 14:03:18 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-05-18 14:03:18 -0700 |
| commit | 7f99954970001cfc1b155d877ac2966d77e2c647 (patch) | |
| tree | 585e05cfeb9fc8e287b7b607bc27851b90ebf30c /include/elf | |
| parent | 400174b12a46fffbfad7c2504c33bb3ac29f3ef9 (diff) | |
| download | gdb-7f99954970001cfc1b155d877ac2966d77e2c647.zip gdb-7f99954970001cfc1b155d877ac2966d77e2c647.tar.gz gdb-7f99954970001cfc1b155d877ac2966d77e2c647.tar.bz2 | |
RISC-V: Add RV32E support.
Kito Cheng <kito.cheng@gmail.com>
Monk Chiang <sh.chiang04@gmail.com>
bfd/
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle
EF_RISCV_RVE.
binutils/
* readelf.c (get_machine_flags): Handle EF_RISCV_RVE.
gas/
* config/tc-riscv.c (rve_abi): New.
(riscv_set_options): Add rve field. Initialize it.
(riscv_set_rve) New function.
(riscv_set_arch): Support 'e' ISA subset.
(reg_lookup_internal): If rve, check register is available.
(riscv_set_abi): New parameter rve.
(md_parse_option): Pass new argument to riscv_set_abi.
(riscv_after_parse_args): Call riscv_set_rve. If rve_abi, set
EF_RISCV_RVE.
* doc/c-riscv.texi (-mabi): Document new ilp32e argument.
include/
* elf/riscv.h (EF_RISCV_RVE): New define.
Diffstat (limited to 'include/elf')
| -rw-r--r-- | include/elf/riscv.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/elf/riscv.h b/include/elf/riscv.h index defbbf4..d036e83 100644 --- a/include/elf/riscv.h +++ b/include/elf/riscv.h @@ -110,6 +110,9 @@ END_RELOC_NUMBERS (R_RISCV_max) /* File uses the quad-float ABI. */ #define EF_RISCV_FLOAT_ABI_QUAD 0x0006 +/* File uses the 32E base integer instruction. */ +#define EF_RISCV_RVE 0x0008 + /* The name of the global pointer symbol. */ #define RISCV_GP_SYMBOL "__global_pointer$" |