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authorNick Clifton <nickc@redhat.com>1999-07-17 15:40:17 +0000
committerNick Clifton <nickc@redhat.com>1999-07-17 15:40:17 +0000
commitc2c594b87d1ac69a17450b5d523562420a113023 (patch)
treef3600740a7f287d5f74e7d17b16a40ed295733f6 /include/coff
parente76d716a43077dda76f2c3cdf5855d9beeb259e3 (diff)
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Rename F_SOFTFLOAt to F_SOFT_FLOAT for compatability with include/elf/arm.h
Diffstat (limited to 'include/coff')
-rw-r--r--include/coff/ChangeLog4
-rw-r--r--include/coff/arm.h7
2 files changed, 6 insertions, 5 deletions
diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog
index c8e67f1..659dcdc 100644
--- a/include/coff/ChangeLog
+++ b/include/coff/ChangeLog
@@ -1,3 +1,7 @@
+1999-07-17 Nick Clifton <nickc@cygnus.com>
+
+ * arm.h (F_SOFT_FLOAT): Rename from F_SOFTFLOAT.
+
1999-06-21 Philip Blundell <pb@nexus.co.uk>
* arm.h (F_SOFTFLOAT): Define.
diff --git a/include/coff/arm.h b/include/coff/arm.h
index b7a0013..d5163f8 100644
--- a/include/coff/arm.h
+++ b/include/coff/arm.h
@@ -44,7 +44,7 @@ struct external_filehdr
* F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax)
* F_APCS_26 file uses 26 bit ARM Procedure Calling Standard
* F_APCS_SET the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised
- * F_SOFTFLOAT code does not use floating point instructions
+ * F_SOFT_FLOAT code does not use floating point instructions
*/
#define F_RELFLG (0x0001)
@@ -59,7 +59,7 @@ struct external_filehdr
#define F_AR32WR (0x0100)
#define F_APCS_26 (0x0400)
#define F_APCS_SET (0x0800)
-#define F_SOFTFLOAT (0x2000)
+#define F_SOFT_FLOAT (0x2000)
/* Bits stored in flags field of the internal_f structure */
@@ -262,8 +262,6 @@ union external_auxent
char x_tvlen[2]; /* length of .tv */
char x_tvran[2][2]; /* tv range */
} x_tv; /* info about .tv section (in auxent of symbol .tv)) */
-
-
};
#define SYMENT struct external_syment
@@ -282,6 +280,5 @@ struct external_reloc
char r_offset[4];
};
-
#define RELOC struct external_reloc
#define RELSZ 14