RISC-V: map zext.h to pack/packw if Zbkb is enabled

The `zext.h` is zero-extend halfword instruction that belongs to Zbb.
Currently `zext.h` falls back to 2 shifts if Zbb is not enabled.  However, the
encoding and operation is a special case of `pack/packw rd, rs1, rs2`, which
belongs to Zbkb.  The instructions pack the low halves of rs1 and rs2 into rd.
When rs2 is zero (x0), they behave like zero-extend instruction, and the
encoding are exactly the same as zext.h.

Thus we can map `zext.h` to `pack` or `packw` (rv64) if Zbkb is enabled,
instead of 2 shifts. This reduces one instruction.

This patch does this by making `zext.h` also available for Zbkb.

opcodes/
	* riscv-opc.c (riscv_opcodes): Update `zext.h` entries to use
	`ZBB_OR_ZBKB` instruction class.

gas/
	* testsuite/gas/riscv/zext-to-pack.s: Add test for mapping zext to
	pack/packw encoding.
	* testsuite/gas/riscv/zext-to-pack-encoding.d: Likewise.
	* testsuite/gas/riscv/zext-to-packw-encoding.d: Likewise.

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