diff options
| author | Pierre Muller <muller@sourceware.org> | 2014-11-28 19:21:58 +0400 |
|---|---|---|
| committer | Joel Brobecker <brobecker@adacore.com> | 2014-11-28 19:30:43 +0400 |
| commit | f7ca3fcfccd144c234370aa939e4f5f15f3b2a88 (patch) | |
| tree | 3fec6f3c4b5b6a0331b60d49a74b662ce426e513 /gdb | |
| parent | b2859a9a54fcc824c3ed7948767d095c02570a19 (diff) | |
| download | gdb-f7ca3fcfccd144c234370aa939e4f5f15f3b2a88.zip gdb-f7ca3fcfccd144c234370aa939e4f5f15f3b2a88.tar.gz gdb-f7ca3fcfccd144c234370aa939e4f5f15f3b2a88.tar.bz2 | |
Fix amd64 dwarf register number mapping (MMX register and higher)
Dwarf register numbers are defined in "System V Application Binary
Interface AMD64 Architecture Processor Supplement Draft Version 0.99.6"
The amd64_dwarf_regmap array is missing the 8 MMX registers in Figure
3.36: DWARF Register Number Mapping page 57. This leads to a wrong
value for the registers past this point.
gdb/ChangeLog:
Pushed by Joel Brobecker <brobecker@adacore.com>.
* amd64-tdep.c (amd64_dwarf_regmap array): Add missing MMX
registers.
Tested on x86_64-linux.
Diffstat (limited to 'gdb')
| -rw-r--r-- | gdb/ChangeLog | 6 | ||||
| -rw-r--r-- | gdb/amd64-tdep.c | 8 |
2 files changed, 13 insertions, 1 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 6b5c02a..21e1a7e 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,9 @@ +2014-11-28 Pierre Muller <muller@sourceware.org> + + Pushed by Joel Brobecker <brobecker@adacore.com>. + * amd64-tdep.c (amd64_dwarf_regmap array): Add missing MMX + registers. + 2014-11-28 Ulrich Weigand <uweigand@de.ibm.com> * config/ia64/linux.mh (NATDEPFILES): Remove core-regset.o. diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index e69da01..7bc4694 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -199,7 +199,13 @@ static int amd64_dwarf_regmap[] = AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, - + + /* MMX Registers 0 - 7. + We have to handle those registers specifically, as their register + number within GDB depends on the target (or they may even not be + available at all). */ + -1, -1, -1, -1, -1, -1, -1, -1, + /* Control and Status Flags Register. */ AMD64_EFLAGS_REGNUM, |