diff options
| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-12-13 19:06:23 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-12-22 10:02:20 +0000 |
| commit | ecc82c059059cfa21a8a099779253686f9637f9f (patch) | |
| tree | 7dab3fa09b096efe9452109ed7beb329f302d87c /gdb | |
| parent | fb44d95af64dd0609760c1400b9ce4da09296cd1 (diff) | |
| download | gdb-ecc82c059059cfa21a8a099779253686f9637f9f.zip gdb-ecc82c059059cfa21a8a099779253686f9637f9f.tar.gz gdb-ecc82c059059cfa21a8a099779253686f9637f9f.tar.bz2 | |
gdb/riscv: Add float status registers to save and restore reggroups
We should save and restore the floating point status registers. This
became an issue when testing 32-bit float on a target with 64-bit with
the gdb.base/callfuncs.exp test.
gdb/ChangeLog:
* riscv-tdep.c (riscv_register_reggroup_p): Save and restore fcsr,
fflags, and frm registers.
Diffstat (limited to 'gdb')
| -rw-r--r-- | gdb/ChangeLog | 5 | ||||
| -rw-r--r-- | gdb/riscv-tdep.c | 5 |
2 files changed, 9 insertions, 1 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index ea00361..513bc7c 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,5 +1,10 @@ 2018-12-22 Andrew Burgess <andrew.burgess@embecosm.com> + * riscv-tdep.c (riscv_register_reggroup_p): Save and restore fcsr, + fflags, and frm registers. + +2018-12-22 Andrew Burgess <andrew.burgess@embecosm.com> + * riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function. (riscv_gdbarch_init): Register new function with gdbarch. * riscv-tdep.h: New enum to define RISC-V DWARF register numbers. diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 3408f5a..704e851 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -896,7 +896,10 @@ riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, else if (reggroup == restore_reggroup || reggroup == save_reggroup) { if (riscv_has_fp_regs (gdbarch)) - return regnum <= RISCV_LAST_FP_REGNUM; + return (regnum <= RISCV_LAST_FP_REGNUM + || regnum == RISCV_CSR_FCSR_REGNUM + || regnum == RISCV_CSR_FFLAGS_REGNUM + || regnum == RISCV_CSR_FRM_REGNUM); else return regnum < RISCV_FIRST_FP_REGNUM; } |