diff options
| author | Nelson Chu <nelson.chu@sifive.com> | 2020-03-12 02:48:39 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2020-03-30 12:24:53 -0700 |
| commit | d1a89da5de1e2d15de27c5ca6b575d633c0117dd (patch) | |
| tree | d3a8c02b9a50305e3ed3eb557fdbd27df495f0f2 /gdb | |
| parent | d8af906814bd69dad694e475288401b1dee6ac3a (diff) | |
| download | gdb-d1a89da5de1e2d15de27c5ca6b575d633c0117dd.zip gdb-d1a89da5de1e2d15de27c5ca6b575d633c0117dd.tar.gz gdb-d1a89da5de1e2d15de27c5ca6b575d633c0117dd.tar.bz2 | |
RISC-V: Update CSR to privileged spec 1.11.
gas/
* testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
* testsuite/gas/riscv/alias-csr.s: Likewise.
* testsuite/gas/riscv/no-aliases-csr.d: Move this
to priv-reg-pseudo-noalias.
* testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
* testsuite/gas/riscv/bad-csr.l: Likewise.
* testsuite/gas/riscv/bad-csr.s: Likewise.
* testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
* testsuite/gas/riscv/satp.s: Likewise.
* testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
csr instruction, including alias-csr testcase.
* testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
* testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
pseudo instruction with objdump -Mno-aliases.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
* testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
* testsuite/gas/riscv/priv-reg.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
include/
* opcode/riscv-opc.h: Update CSR to 1.11.
gdb/
* features/riscv/32bit-csr.xml: Regenerated.
* features/riscv/64bit-csr.xml: Regenerated.
Diffstat (limited to 'gdb')
| -rw-r--r-- | gdb/ChangeLog | 5 | ||||
| -rw-r--r-- | gdb/features/riscv/32bit-csr.xml | 5 | ||||
| -rw-r--r-- | gdb/features/riscv/64bit-csr.xml | 5 |
3 files changed, 11 insertions, 4 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index af7e151..67aa872 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2020-03-30 Nelson Chu <nelson.chu@sifive.com> + + * features/riscv/32bit-csr.xml: Regenerated. + * features/riscv/64bit-csr.xml: Regenerated. + 2020-03-30 Tom Tromey <tromey@adacore.com> * ada-valprint.c (print_variant_part): Update. diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml index 5b79499..8173eeb 100644 --- a/gdb/features/riscv/32bit-csr.xml +++ b/gdb/features/riscv/32bit-csr.xml @@ -192,6 +192,7 @@ <reg name="mhpmcounter29h" bitsize="32"/> <reg name="mhpmcounter30h" bitsize="32"/> <reg name="mhpmcounter31h" bitsize="32"/> + <reg name="mcountinhibit" bitsize="32"/> <reg name="mhpmevent3" bitsize="32"/> <reg name="mhpmevent4" bitsize="32"/> <reg name="mhpmevent5" bitsize="32"/> @@ -227,7 +228,8 @@ <reg name="tdata3" bitsize="32"/> <reg name="dcsr" bitsize="32"/> <reg name="dpc" bitsize="32"/> - <reg name="dscratch" bitsize="32"/> + <reg name="dscratch0" bitsize="32"/> + <reg name="dscratch1" bitsize="32"/> <reg name="hstatus" bitsize="32"/> <reg name="hedeleg" bitsize="32"/> <reg name="hideleg" bitsize="32"/> @@ -244,7 +246,6 @@ <reg name="mibound" bitsize="32"/> <reg name="mdbase" bitsize="32"/> <reg name="mdbound" bitsize="32"/> - <reg name="mucounteren" bitsize="32"/> <reg name="mscounteren" bitsize="32"/> <reg name="mhcounteren" bitsize="32"/> </feature> diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml index 8ec0ffe..ed28964 100644 --- a/gdb/features/riscv/64bit-csr.xml +++ b/gdb/features/riscv/64bit-csr.xml @@ -127,6 +127,7 @@ <reg name="mhpmcounter29" bitsize="64"/> <reg name="mhpmcounter30" bitsize="64"/> <reg name="mhpmcounter31" bitsize="64"/> + <reg name="mcountinhibit" bitsize="64"/> <reg name="mhpmevent3" bitsize="64"/> <reg name="mhpmevent4" bitsize="64"/> <reg name="mhpmevent5" bitsize="64"/> @@ -162,7 +163,8 @@ <reg name="tdata3" bitsize="64"/> <reg name="dcsr" bitsize="64"/> <reg name="dpc" bitsize="64"/> - <reg name="dscratch" bitsize="64"/> + <reg name="dscratch0" bitsize="64"/> + <reg name="dscratch1" bitsize="64"/> <reg name="hstatus" bitsize="64"/> <reg name="hedeleg" bitsize="64"/> <reg name="hideleg" bitsize="64"/> @@ -179,7 +181,6 @@ <reg name="mibound" bitsize="64"/> <reg name="mdbase" bitsize="64"/> <reg name="mdbound" bitsize="64"/> - <reg name="mucounteren" bitsize="64"/> <reg name="mscounteren" bitsize="64"/> <reg name="mhcounteren" bitsize="64"/> </feature> |