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| author | Mike Frysinger <vapier@gentoo.org> | 2015-06-16 21:29:48 +0545 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-02-04 19:15:17 -0500 |
| commit | 04b4939b0362686e7b3ebb531edb0bbd37a59a1b (patch) | |
| tree | dc22e1672494f5271721ef6df42c41b4dae3afc8 /gdb | |
| parent | b9249c461c72b35dd9b6f274406c336f6a68ae98 (diff) | |
| download | gdb-04b4939b0362686e7b3ebb531edb0bbd37a59a1b.zip gdb-04b4939b0362686e7b3ebb531edb0bbd37a59a1b.tar.gz gdb-04b4939b0362686e7b3ebb531edb0bbd37a59a1b.tar.bz2 | |
gdb: riscv: enable sim integration
Now the simulator can be loaded via gdb using "target sim".
Diffstat (limited to 'gdb')
| -rw-r--r-- | gdb/ChangeLog | 4 | ||||
| -rw-r--r-- | gdb/configure.tgt | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 4078e0e..d729b0e 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,7 @@ +2021-02-04 Mike Frysinger <vapier@gentoo.org> + + * configure.tgt (riscv*-*-*): Set gdb_sim. + 2021-02-04 Simon Marchi <simon.marchi@polymtl.ca> * target.c (target_is_non_stop_p): Return bool. diff --git a/gdb/configure.tgt b/gdb/configure.tgt index 6e03983..5440780 100644 --- a/gdb/configure.tgt +++ b/gdb/configure.tgt @@ -554,6 +554,7 @@ riscv*-*-linux*) riscv*-*-*) # Target: RISC-V architecture gdb_target_obs="" + gdb_sim=../sim/riscv/libsim.a ;; rl78-*-elf) |