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| author | Jaydeep Patil <jaydeep.patil@imgtec.com> | 2024-02-01 04:42:27 +0000 |
|---|---|---|
| committer | Andrew Burgess <aburgess@redhat.com> | 2024-02-13 11:04:04 +0000 |
| commit | 3224e32fb84f034d190ad91d7b9ac86f6800d47a (patch) | |
| tree | 239a301674c7c5040bda776596521d61b83b33ad /gdb/varobj.c | |
| parent | 4dad3c1e1c9e789addc0d196cef8e8ea22ddbeda (diff) | |
| download | gdb-3224e32fb84f034d190ad91d7b9ac86f6800d47a.zip gdb-3224e32fb84f034d190ad91d7b9ac86f6800d47a.tar.gz gdb-3224e32fb84f034d190ad91d7b9ac86f6800d47a.tar.bz2 | |
sim: riscv: Add support for compressed integer instructions
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.
Approved-By: Andrew Burgess <aburgess@redhat.com>
Diffstat (limited to 'gdb/varobj.c')
0 files changed, 0 insertions, 0 deletions