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| author | Robert Suchanek <robert.suchanek@mips.com> | 2019-04-09 17:30:26 +0800 |
|---|---|---|
| committer | Chenghua Xu <paul.hua.gm@gmail.com> | 2019-04-09 09:56:48 +0000 |
| commit | 7e96e219a4fc703282ea5b0cc8845a96c01ca030 (patch) | |
| tree | 5407cdb45929c212b56e239ccf81dc933894fb61 /gdb/testsuite/gdb.base | |
| parent | 2b0c8b019996b23fb4717687f5e7ac8c5620c089 (diff) | |
| download | gdb-7e96e219a4fc703282ea5b0cc8845a96c01ca030.zip gdb-7e96e219a4fc703282ea5b0cc8845a96c01ca030.tar.gz gdb-7e96e219a4fc703282ea5b0cc8845a96c01ca030.tar.bz2 | |
[MIPS] Add RDHWR with the SEL field for MIPS R6.
In Release 6 of the MIPS architecture [1], instruction RDHWR supports
a 3rd operand to serve as the 3-bit select field for the hardware
register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 332-334
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
gas/
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
Diffstat (limited to 'gdb/testsuite/gdb.base')
0 files changed, 0 insertions, 0 deletions