[PowerPC] Aliases for vector registers

This patch defines pseudo-registers "v0" through "v31" as aliases that
map to the corresponding raw "vr0" through "vr31" vector registers for
Power.

The motivation behind this is that although GDB defines these
registers as "vrX", the disassembler prints them as "vX", e.g. as the
operands in instructions such as "vaddubm v2,v1,v1".  This can be
confusing to users trying to print out the values of the operands
while inspecting the disassembled code.

The new aliases are made not to belong to any register group, to avoid
duplicated values in "info register vector" and "info register all".
The arch-specific rs6000_pseudo_register_reggroup_p function had
previously been removed since the other pseudo-registers could have
their groups inferred by their type.  It restored with this patch to
handle the aliases.  Membership for the other pseudo-registers is
still determined using the default function.

A new tests checks that GDB prints the expected values of vector
registers after they are filled by the inferior, by using both the raw
names and the aliases.  Two other existing tests are modified to also
test the aliases.

gdb/ChangeLog:
2019-01-14  Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>

	* ppc-tdep.h (struct gdbarch_tdep) <ppc_v0_alias_regnum>: New
	field.
	* rs6000-tdep.c: Include reggroups.h.
	(IS_V_ALIAS_PSEUDOREG): Define.
	(rs6000_register_name): Return names for the "vX" aliases.
	(rs6000_pseudo_register_type): Return type for the "vX" aliases.
	(rs6000_pseudo_register_reggroup_p): Restore.  Handle "vX"
	aliases.  Call default_register_reggroup_p for all other
	pseudo-registers.
	(v_alias_pseudo_register_read, v_alias_pseudo_register_write):
	New functions.
	(rs6000_pseudo_register_read, rs6000_pseudo_register_write):
	Handle "vX" aliases.
	(v_alias_pseudo_register_collect): New function.
	(rs6000_ax_pseudo_register_collect): Handle "vX" aliases.
	(rs6000_gdbarch_init): Initialize "vX" aliases as
	pseudo-registers.  Restore registration of
	rs6000_pseudo_register_reggroup_p with
	set_tdesc_pseudo_register_reggroup_p.

gdb/testsuite/ChangeLog:
2019-01-14  Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>

	* gdb.arch/vsx-regs.exp: Add tests that use the vector register
	aliases.
	* gdb.arch/altivec-regs.exp: Likewise.  Fix indentation of two
	tests.
	* gdb.arch/powerpc-vector-regs.c: New file.
	* gdb.arch/powerpc-vector-regs.exp: New file.

gdb/doc/ChangeLog:
2019-01-14  Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>

	* gdb.texinfo (PowerPC Features): Document the alias
	pseudo-registers for the org.gnu.gdb.power.altivec feature.

1 files changed, 3 insertions, 0 deletions

diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp
index 2454aee..d2fa612 100644
--- a/gdb/testsuite/gdb.arch/vsx-regs.exp
+++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
@@ -136,6 +136,7 @@ for {set i 32} {$i < 64} {incr i 1} {
 
 for {set i 0} {$i < 32} {incr i 1} {
     gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
+    gdb_test "info reg v$i" "v$i.*$vector_register3_vr" "info reg v$i"
 }
 
 # Create a core file.  We create the core file before the F32~F63/VR0~VR31 test
@@ -155,6 +156,7 @@ for {set i 32} {$i < 64} {incr i 1} {
 
 for {set i 0} {$i < 32} {incr i 1} {
     gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
+    gdb_test "info reg v$i" "v$i.*$vector_register1_vr" "info reg v$i (doubleword 0)"
 }
 
 # 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
@@ -170,6 +172,7 @@ for {set i 32} {$i < 64} {incr i 1} {
 
 for {set i 0} {$i < 32} {incr i 1} {
     gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
+    gdb_test "info reg v$i" "v$i.*$vector_register2_vr" "info reg v$i (doubleword 1)"
 }
 
 # Test reading the core file.