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authorSimon Marchi <simon.marchi@efficios.com>2023-03-09 14:56:09 -0500
committerSimon Marchi <simon.marchi@efficios.com>2023-03-09 16:32:00 -0500
commit287de65625a667b6403d0606fa75b67926ec7230 (patch)
treea4911b3dc540ba6a54e0aebbbe972cec6f1d8be1 /gdb/rs6000-tdep.c
parent2562954ede66f32bff7d985e752b8052c2ae5775 (diff)
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gdb, gdbserver, gdbsupport: fix whitespace issues
Replace spaces with tabs in a bunch of places. Change-Id: If0f87180f1d13028dc178e5a8af7882a067868b0
Diffstat (limited to 'gdb/rs6000-tdep.c')
-rw-r--r--gdb/rs6000-tdep.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 104515d..6ba5652 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -1058,7 +1058,7 @@ ppc_displaced_step_fixup (struct gdbarch *gdbarch,
else
{
/* Handle any other instructions that do not fit in the categories
- above. */
+ above. */
regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
from + offset);
}
@@ -4181,15 +4181,15 @@ ppc_record_ACC_fpscr (struct regcache *regcache, ppc_gdbarch_tdep *tdep,
entry consist of four 128-bit rows.
The ACC rows map to specific VSR registers.
- ACC[0][0] -> VSR[0]
- ACC[0][1] -> VSR[1]
- ACC[0][2] -> VSR[2]
- ACC[0][3] -> VSR[3]
- ...
- ACC[7][0] -> VSR[28]
- ACC[7][1] -> VSR[29]
- ACC[7][2] -> VSR[30]
- ACC[7][3] -> VSR[31]
+ ACC[0][0] -> VSR[0]
+ ACC[0][1] -> VSR[1]
+ ACC[0][2] -> VSR[2]
+ ACC[0][3] -> VSR[3]
+ ...
+ ACC[7][0] -> VSR[28]
+ ACC[7][1] -> VSR[29]
+ ACC[7][2] -> VSR[30]
+ ACC[7][3] -> VSR[31]
NOTE:
In ISA 3.1 the ACC is mapped on top of VSR[0] thru VSR[31].
@@ -7446,14 +7446,14 @@ rs6000_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address)
if (target_read_memory (address, target_mem, PPC_INSN_SIZE) == 0)
{
uint32_t insn = (uint32_t) extract_unsigned_integer
- (target_mem, PPC_INSN_SIZE, gdbarch_byte_order_for_code (gdbarch));
+ (target_mem, PPC_INSN_SIZE, gdbarch_byte_order_for_code (gdbarch));
/* Check if INSN is a TW, TWI, TD or TDI instruction. There
- are multiple choices of such instructions with different registers
- and / or immediate values but they all cause a break. */
+ are multiple choices of such instructions with different registers
+ and / or immediate values but they all cause a break. */
if (is_tw_insn (insn) || is_twi_insn (insn) || is_td_insn (insn)
- || is_tdi_insn (insn))
- return true;
+ || is_tdi_insn (insn))
+ return true;
}
return false;
@@ -8326,7 +8326,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
set_gdbarch_sw_breakpoint_from_kind (gdbarch,
rs6000_breakpoint::bp_from_kind);
set_gdbarch_program_breakpoint_here_p (gdbarch,
- rs6000_program_breakpoint_here_p);
+ rs6000_program_breakpoint_here_p);
/* The value of symbols of type N_SO and N_FUN maybe null when
it shouldn't be. */