diff options
| author | Tom Tromey <tromey@adacore.com> | 2019-04-19 10:41:40 -0600 |
|---|---|---|
| committer | Tom Tromey <tromey@adacore.com> | 2019-12-12 11:47:40 -0700 |
| commit | db3ad2f031d4da70db35977abbcede0399d81d6b (patch) | |
| tree | d1f99732683aad6b7ff3c45a573668215d7f86c6 /gdb/riscv-tdep.c | |
| parent | 2ffe5b9c792fe78dbbcbe31b6fea751285df8876 (diff) | |
| download | gdb-db3ad2f031d4da70db35977abbcede0399d81d6b.zip gdb-db3ad2f031d4da70db35977abbcede0399d81d6b.tar.gz gdb-db3ad2f031d4da70db35977abbcede0399d81d6b.tar.bz2 | |
Ravenscar port for RISC-V
This adds Ravenscar support to gdb for RISC-V targets.
This was tested internally using AdaCore's test suite and qemu.
gdb/ChangeLog
2019-12-12 Tom Tromey <tromey@adacore.com>
* Makefile.in (ALL_TARGET_OBS): Add riscv-ravenscar-thread.o.
(HFILES_NO_SRCDIR): Add riscv-ravenscar-thread.h.
(ALLDEPFILES): Add riscv-ravenscar-thread.c.
* configure.tgt (riscv-*-*): Add riscv-ravenscar-thread.o.
* riscv-ravenscar-thread.c: New file.
* riscv-ravenscar-thread.h: New file.
* riscv-tdep.c (riscv_gdbarch_init): Call
register_riscv_ravenscar_ops.
Change-Id: Ic47a3b3cfbbe80c2c82a5f48d2e0481845cac8b0
Diffstat (limited to 'gdb/riscv-tdep.c')
| -rw-r--r-- | gdb/riscv-tdep.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index d262b7d..a8b057f 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -56,6 +56,7 @@ #include "observable.h" #include "prologue-value.h" #include "arch/riscv.h" +#include "riscv-ravenscar-thread.h" /* The stack must be 16-byte aligned. */ #define SP_ALIGNMENT 16 @@ -3358,6 +3359,8 @@ riscv_gdbarch_init (struct gdbarch_info info, /* Hook in OS ABI-specific overrides, if they have been registered. */ gdbarch_init_osabi (info, gdbarch); + register_riscv_ravenscar_ops (gdbarch); + return gdbarch; } |