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authorJaydeep Patil <jaydeep.patil@imgtec.com>2024-02-01 04:42:27 +0000
committerAndrew Burgess <aburgess@redhat.com>2024-02-13 11:04:04 +0000
commit3224e32fb84f034d190ad91d7b9ac86f6800d47a (patch)
tree239a301674c7c5040bda776596521d61b83b33ad /gdb/probe.h
parent4dad3c1e1c9e789addc0d196cef8e8ea22ddbeda (diff)
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sim: riscv: Add support for compressed integer instructions
Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>
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