Change return type of gdbarch_software_single_step to vector<CORE_ADDR>

This is a relatively straightforward patch that changes
gdbarch_software_single_step so it returns an std::vector<CORE_ADDR>
instead of a VEC (CORE_ADDR).

gdb/ChangeLog:

	* gdbarch.sh (software_single_step): Change return type to
	std::vector<CORE_ADDR>.
	* gdbarch.c, gdbarch.h: Re-generate.
	* arch/arm-get-next-pcs.c (thumb_deal_with_atomic_sequence_raw):
	Adjust.
	(arm_deal_with_atomic_sequence_raw): Adjust.
	(thumb_get_next_pcs_raw): Adjust.
	(arm_get_next_pcs_raw): Adjust.
	(arm_get_next_pcs): Adjust.
	* arch/arm-get-next-pcs.h (arm_get_next_pcs): Adjust.
	* aarch64-tdep.c (aarch64_software_single_step): Adjust.
	* alpha-tdep.c (alpha_deal_with_atomic_sequence): Adjust.
	(alpha_software_single_step): Adjust.
	* alpha-tdep.h (alpha_software_single_step): Adjust.
	* arm-linux-tdep.c (arm_linux_software_single_step): Adjust.
	* arm-tdep.c (arm_software_single_step): Adjust.
	(arm_breakpoint_kind_from_current_state): Adjust.
	* arm-tdep.h (arm_software_single_step): Adjust.
	* breakpoint.c (insert_single_step_breakpoint): Adjust.
	* cris-tdep.c (cris_software_single_step): Adjust.
	* mips-tdep.c (mips_deal_with_atomic_sequence): Adjust.
	(micromips_deal_with_atomic_sequence): Adjust.
	(deal_with_atomic_sequence): Adjust.
	(mips_software_single_step): Adjust.
	* mips-tdep.h (mips_software_single_step): Adjust.
	* moxie-tdep.c (moxie_software_single_step): Adjust.
	* nios2-tdep.c (nios2_software_single_step): Adjust.
	* ppc-tdep.h (ppc_deal_with_atomic_sequence): Adjust.
	* rs6000-aix-tdep.c (rs6000_software_single_step): Adjust.
	* rs6000-tdep.c (ppc_deal_with_atomic_sequence): Adjust.
	* s390-linux-tdep.c (s390_software_single_step): Adjust.
	* sparc-tdep.c (sparc_software_single_step): Adjust.
	* spu-tdep.c (spu_software_single_step): Adjust.
	* tic6x-tdep.c (tic6x_software_single_step): Adjust.

gdb/gdbserver/ChangeLog:

	* linux-arm-low.c (arm_gdbserver_get_next_pcs): Adjust to
	software_single_step change of return type to
	std::vector<CORE_ADDR>.
	* linux-low.c (install_software_single_step_breakpoints):
	Likewise.
	* linux-low.h (install_software_single_step_breakpoints):
	Likewise.

1 files changed, 29 insertions, 28 deletions

diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index 2364c2e..f8e6809 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -3879,7 +3879,7 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
 #define SC_OPCODE 0x38
 #define SCD_OPCODE 0x3c
 
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
 {
   CORE_ADDR breaks[2] = {-1, -1};
@@ -3890,12 +3890,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
   int index;
   int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed).  */  
   const int atomic_sequence_length = 16; /* Instruction sequence length.  */
-  VEC (CORE_ADDR) *next_pcs = NULL;
 
   insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
   /* Assume all atomic sequences start with a ll/lld instruction.  */
   if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
-    return NULL;
+    return {};
 
   /* Assume that no atomic sequence is longer than "atomic_sequence_length" 
      instructions.  */
@@ -3912,7 +3911,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
 	{
 	case 0: /* SPECIAL */
 	  if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
-	    return 0; /* fallback to the standard single-step code.  */
+	    return {}; /* fallback to the standard single-step code.  */
 	  break;
 	case 1: /* REGIMM */
 	  is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */
@@ -3921,7 +3920,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
 	  break;
 	case 2: /* J */
 	case 3: /* JAL */
-	  return 0; /* fallback to the standard single-step code.  */
+	  return {}; /* fallback to the standard single-step code.  */
 	case 4: /* BEQ */
 	case 5: /* BNE */
 	case 6: /* BLEZ */
@@ -3947,8 +3946,8 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
 	{
 	  branch_bp = loc + mips32_relative_offset (insn) + 4;
 	  if (last_breakpoint >= 1)
-	    return 0; /* More than one branch found, fallback to the
-			 standard single-step code.  */
+	    return {}; /* More than one branch found, fallback to the
+			  standard single-step code.  */
 	  breaks[1] = branch_bp;
 	  last_breakpoint++;
 	}
@@ -3959,7 +3958,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
 
   /* Assume that the atomic sequence ends with a sc/scd instruction.  */
   if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
-    return NULL;
+    return {};
 
   loc += MIPS_INSN32_SIZE;
 
@@ -3971,14 +3970,16 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
   if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
     last_breakpoint = 0;
 
+  std::vector<CORE_ADDR> next_pcs;
+
   /* Effectively inserts the breakpoints.  */
   for (index = 0; index <= last_breakpoint; index++)
-    VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+    next_pcs.push_back (breaks[index]);
 
   return next_pcs;
 }
 
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
 				     CORE_ADDR pc)
 {
@@ -3992,17 +3993,16 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
   ULONGEST insn;
   int insn_count;
   int index;
-  VEC (CORE_ADDR) *next_pcs = NULL;
 
   /* Assume all atomic sequences start with a ll/lld instruction.  */
   insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
   if (micromips_op (insn) != 0x18)	/* POOL32C: bits 011000 */
-    return NULL;
+    return {};
   loc += MIPS_INSN16_SIZE;
   insn <<= 16;
   insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
   if ((b12s4_op (insn) & 0xb) != 0x3)	/* LL, LLD: bits 011000 0x11 */
-    return NULL;
+    return {};
   loc += MIPS_INSN16_SIZE;
 
   /* Assume all atomic sequences end with an sc/scd instruction.  Assume
@@ -4072,7 +4072,7 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
 	    case 0x35: /* J: bits 110101 */
 	    case 0x3d: /* JAL: bits 111101 */
 	    case 0x3c: /* JALX: bits 111100 */
-	      return 0; /* Fall back to the standard single-step code. */
+	      return {}; /* Fall back to the standard single-step code. */
 
 	    case 0x18: /* POOL32C: bits 011000 */
 	      if ((b12s4_op (insn) & 0xb) == 0xb)
@@ -4099,24 +4099,24 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
 	          && b5s5_op (insn) != 0x18)
 				/* JRADDIUSP: bits 010001 11000 */
 	        break;
-	      return NULL; /* Fall back to the standard single-step code. */
+	      return {}; /* Fall back to the standard single-step code. */
 
 	    case 0x33: /* B16: bits 110011 */
-	      return NULL; /* Fall back to the standard single-step code. */
+	      return {}; /* Fall back to the standard single-step code. */
 	    }
 	  break;
 	}
       if (is_branch)
 	{
 	  if (last_breakpoint >= 1)
-	    return NULL; /* More than one branch found, fallback to the
-			 standard single-step code.  */
+	    return {}; /* More than one branch found, fallback to the
+			  standard single-step code.  */
 	  breaks[1] = branch_bp;
 	  last_breakpoint++;
 	}
     }
   if (!sc_found)
-    return NULL;
+    return {};
 
   /* Insert a breakpoint right after the end of the atomic sequence.  */
   breaks[0] = loc;
@@ -4126,14 +4126,16 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
   if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
     last_breakpoint = 0;
 
+  std::vector<CORE_ADDR> next_pcs;
+
   /* Effectively inserts the breakpoints.  */
   for (index = 0; index <= last_breakpoint; index++)
-    VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+    next_pcs.push_back (breaks[index]);
 
   return next_pcs;
 }
 
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
 deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
 {
   if (mips_pc_is_mips (pc))
@@ -4141,7 +4143,7 @@ deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
   else if (mips_pc_is_micromips (gdbarch, pc))
     return micromips_deal_with_atomic_sequence (gdbarch, pc);
   else
-    return NULL;
+    return {};
 }
 
 /* mips_software_single_step() is called just before we want to resume
@@ -4149,22 +4151,21 @@ deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
    or kernel single-step support (MIPS on GNU/Linux for example).  We find
    the target of the coming instruction and breakpoint it.  */
 
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
 mips_software_single_step (struct regcache *regcache)
 {
   struct gdbarch *gdbarch = get_regcache_arch (regcache);
   CORE_ADDR pc, next_pc;
-  VEC (CORE_ADDR) *next_pcs;
 
   pc = regcache_read_pc (regcache);
-  next_pcs = deal_with_atomic_sequence (gdbarch, pc);
-  if (next_pcs != NULL)
+  std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc);
+
+  if (!next_pcs.empty ())
     return next_pcs;
 
   next_pc = mips_next_pc (regcache, pc);
 
-  VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
-  return next_pcs;
+  return {next_pc};
 }
 
 /* Test whether the PC points to the return instruction at the