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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2023-07-07 12:58:34 +0300 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gmail.com> | 2023-07-07 13:08:04 +0300 |
| commit | 13aa307c9a9086d34b555cecf5f9388fa9b062f1 (patch) | |
| tree | 4de500818ab17496162d8f65bb7c3d6ef42c7190 /gdb/m2-exp.h | |
| parent | 7c632c2a696fb68e5575db1e2c934788a831e578 (diff) | |
| download | gdb-13aa307c9a9086d34b555cecf5f9388fa9b062f1.zip gdb-13aa307c9a9086d34b555cecf5f9388fa9b062f1.tar.gz gdb-13aa307c9a9086d34b555cecf5f9388fa9b062f1.tar.bz2 | |
arc: Update/Add ARCv3 support.
The ARC HS5x and ARC HS6x processors are based on the new ARCv3 ISA
that implements a full range of 32-bit and 64-bit instructions. These
processors feature a high-speed 10-stage, dual-issue pipeline that
offers increased utilization of functional units with a limited
increase in power and area. The HS5x processors feature a 32-bit
pipeline that can execute all ARCv3 32-bit instructions, while the
HS6x processors feature a full 64-bit pipeline and register file that
can execute both 32-bit and 64-bit instructions. In addition, the ARC
HS6x supports 64-bit virtual and 52-bit physical address spaces to
enable direct addressing of current and future large memories, as well
as 128-bit loads and stores for efficient data movement.
This readelf patch updates/adds Synopsys ARCv3 machine name fileds and
supported relocations.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Diffstat (limited to 'gdb/m2-exp.h')
0 files changed, 0 insertions, 0 deletions