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authorMaciej W. Rozycki <macro@orcam.me.uk>2024-09-15 15:28:18 +0100
committerMaciej W. Rozycki <macro@orcam.me.uk>2024-09-15 15:28:18 +0100
commitc26846ab066fc6e3a2843cbadfe159e0c4a1cc21 (patch)
treed04790008bec76bbdd70b7e2a30d3d57a070aff7 /gdb/gdbserver/regcache.c
parent248f96fba6fd0db5f56d1133a6655a15954b648f (diff)
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MIPS/GAS: Discard redundant instruction from DDIV/DREM macrosHEADmaster
A sequence such as: li at,-1 bne xx,at,0f li at,1 dsll32 at,at,0x1f is produced in the expansion of the DDIV and DREM assembly macros, where a redundant `li at,1' instruction is used to load an intermediate value of 1 into $at, which is then left-shifted by 63 with `dsll32 at,at,0x1f' yielding 0x8000000000000000. However this value likewise results from left-shifting the value of -1, already present in $at at this point. Remove the extraneous instruction then, shortening the sequence emitted. Adjust dumps in the testsuite accordingly.
Diffstat (limited to 'gdb/gdbserver/regcache.c')
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