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| author | Yao Qi <yao.qi@linaro.org> | 2016-04-22 15:53:05 +0100 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2016-04-22 15:54:43 +0100 |
| commit | 3539aa13fbcadd930b0b6d8a97f9f125f02a73dc (patch) | |
| tree | 6518aa835631d8c4a65391b9f2d1f3ff2290f125 /gdb/gdbserver/ChangeLog | |
| parent | 495346f6f07ea711662106f0e6f8d684fe489cd8 (diff) | |
| download | gdb-3539aa13fbcadd930b0b6d8a97f9f125f02a73dc.zip gdb-3539aa13fbcadd930b0b6d8a97f9f125f02a73dc.tar.gz gdb-3539aa13fbcadd930b0b6d8a97f9f125f02a73dc.tar.bz2 | |
[ARM] Clear reserved bits in CPSR
Bits 20 ~ 23 of CPSR are reserved (RAZ, read as zero), but they are not
zero if the arm program runs on aarch64-linux. AArch64 tracer gets PSTATE
from arm 32-bit tracee as CPSR, but bits 20 ~ 23 are used in PSTATE. I
think kernel should clear these bits when it is read through ptrace, but
the fix in user space is still needed.
This patch fixes these two fails,
-FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr d7, [r11, #-12]
-FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr d7, [r7]
gdb:
2016-04-22 Yao Qi <yao.qi@linaro.org>
* aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR
bits 20 to 23.
gdb/gdbserver:
2016-04-22 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20
to 23.
Diffstat (limited to 'gdb/gdbserver/ChangeLog')
| -rw-r--r-- | gdb/gdbserver/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog index e0ed616..a7ffbf8 100644 --- a/gdb/gdbserver/ChangeLog +++ b/gdb/gdbserver/ChangeLog @@ -1,5 +1,10 @@ 2016-04-22 Yao Qi <yao.qi@linaro.org> + * linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20 + to 23. + +2016-04-22 Yao Qi <yao.qi@linaro.org> + * linux-low.c (lwp_signal_can_be_delivered): Don't deliver signal when stepping over breakpoint with software single step. |