gdb/csky add cskyv2-linux.xml for cskyv2-linux.c

Add cskyv2-linux.xml for re-generating cskyv2-linux.c if needed.
Also update cskyv2-linux.c.

1 files changed, 102 insertions, 0 deletions

diff --git a/gdb/features/cskyv2-linux.xml b/gdb/features/cskyv2-linux.xml
new file mode 100644
index 0000000..d4d45c3
--- /dev/null
+++ b/gdb/features/cskyv2-linux.xml
@@ -0,0 +1,102 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.csky.abiv2">
+  <reg name="r0"  bitsize="32" regnum="0"/>
+  <reg name="r1"  bitsize="32"/>
+  <reg name="r2"  bitsize="32"/>
+  <reg name="r3"  bitsize="32"/>
+  <reg name="r4"  bitsize="32"/>
+  <reg name="r5"  bitsize="32"/>
+  <reg name="r6"  bitsize="32"/>
+  <reg name="r7"  bitsize="32"/>
+  <reg name="r8"  bitsize="32"/>
+  <reg name="r9"  bitsize="32"/>
+  <reg name="r10" bitsize="32"/>
+  <reg name="r11" bitsize="32"/>
+  <reg name="r12" bitsize="32"/>
+  <reg name="r13" bitsize="32"/>
+  <reg name="r14" bitsize="32" type="data_ptr"/>
+  <reg name="r15" bitsize="32"/>
+  <reg name="r16" bitsize="32"/>
+  <reg name="r17" bitsize="32"/>
+  <reg name="r18" bitsize="32"/>
+  <reg name="r19" bitsize="32"/>
+  <reg name="r20" bitsize="32"/>
+  <reg name="r21" bitsize="32"/>
+  <reg name="r22" bitsize="32"/>
+  <reg name="r23" bitsize="32"/>
+  <reg name="r24" bitsize="32"/>
+  <reg name="r25" bitsize="32"/>
+  <reg name="r26" bitsize="32"/>
+  <reg name="r27" bitsize="32"/>
+  <reg name="r28" bitsize="32"/>
+  <reg name="r29" bitsize="32"/>
+  <reg name="r30" bitsize="32"/>
+  <reg name="r31" bitsize="32"/>
+
+  <reg name="hi" bitsize="32" regnum="36"/>
+  <reg name="lo" bitsize="32"/>
+
+  <reg name="fr0"  bitsize="64" type="ieee_double" regnum="40"/>
+  <reg name="fr1"  bitsize="64" type="ieee_double"/>
+  <reg name="fr2"  bitsize="64" type="ieee_double"/>
+  <reg name="fr3"  bitsize="64" type="ieee_double"/>
+  <reg name="fr4"  bitsize="64" type="ieee_double"/>
+  <reg name="fr5"  bitsize="64" type="ieee_double"/>
+  <reg name="fr6"  bitsize="64" type="ieee_double"/>
+  <reg name="fr7"  bitsize="64" type="ieee_double"/>
+  <reg name="fr8"  bitsize="64" type="ieee_double"/>
+  <reg name="fr9"  bitsize="64" type="ieee_double"/>
+  <reg name="fr10" bitsize="64" type="ieee_double"/>
+  <reg name="fr11" bitsize="64" type="ieee_double"/>
+  <reg name="fr12" bitsize="64" type="ieee_double"/>
+  <reg name="fr13" bitsize="64" type="ieee_double"/>
+  <reg name="fr14" bitsize="64" type="ieee_double"/>
+  <reg name="fr15" bitsize="64" type="ieee_double"/>
+
+  <vector id="v4f"   type="ieee_single" count="4"/>
+  <vector id="v2d"   type="ieee_double" count="2"/>
+  <vector id="v16i8" type="int8" count="16"/>
+  <vector id="v8i16" type="int16" count="8"/>
+  <vector id="v4i32" type="int32" count="4"/>
+  <vector id="v2i64" type="int64" count="2"/>
+  <union id="vec128">
+    <field name="v4_float"  type="v4f"/>
+    <field name="v2_double" type="v2d"/>
+    <field name="v16_int8"  type="v16i8"/>
+    <field name="v8_int16"  type="v8i16"/>
+    <field name="v4_int32"  type="v4i32"/>
+    <field name="v2_int64"  type="v2i64"/>
+    <field name="uint128"   type="uint128"/>
+  </union>
+  <reg name="vr0"  bitsize="128" type="vec128" regnum="56"/>
+  <reg name="vr1"  bitsize="128" type="vec128"/>
+  <reg name="vr2"  bitsize="128" type="vec128"/>
+  <reg name="vr3"  bitsize="128" type="vec128"/>
+  <reg name="vr4"  bitsize="128" type="vec128"/>
+  <reg name="vr5"  bitsize="128" type="vec128"/>
+  <reg name="vr6"  bitsize="128" type="vec128"/>
+  <reg name="vr7"  bitsize="128" type="vec128"/>
+  <reg name="vr8"  bitsize="128" type="vec128"/>
+  <reg name="vr9"  bitsize="128" type="vec128"/>
+  <reg name="vr10" bitsize="128" type="vec128"/>
+  <reg name="vr11" bitsize="128" type="vec128"/>
+  <reg name="vr12" bitsize="128" type="vec128"/>
+  <reg name="vr13" bitsize="128" type="vec128"/>
+  <reg name="vr14" bitsize="128" type="vec128"/>
+  <reg name="vr15" bitsize="128" type="vec128"/>
+
+  <reg name="pc"   bitsize="32" type="code_ptr" regnum="72"/>
+  <reg name="psr"  bitsize="32" regnum="89"/>
+
+  <reg name="fid"  bitsize="32" regnum="121"/>
+  <reg name="fcr"  bitsize="32"/>
+  <reg name="fesr" bitsize="32"/>
+  <reg name="usp"  bitsize="32" regnum="127"/>
+</feature>