gdb: Add OpenRISC or1k and or1knd target support

This patch prepares the current GDB port of the OpenRISC processor from
https://github.com/openrisc/binutils-gdb for upstream merging.

Testing has been done with a cgen sim provided in a separate patch. This
has been tested with 2 toolchains. GCC [1] 5.4.0 from the OpenRISC
project with Newlib [2] and GCC 5.4.0 with Musl [3] 1.1.4.

It supports or1knd (no delay slot target).
The default target is or1k (with delay slot).

You can change the target arch with:

(gdb) set architecture or1knd
The target architecture is assumed to be or1knd

[1] https://github.com/openrisc/or1k-gcc
[2] https://github.com/openrisc/newlib
[3] https://github.com/openrisc/musl-cross

gdb/doc/ChangeLog:

2017-12-12  Stafford Horne  <shorne@gmail.com>
	    Stefan Wallentowitz  <stefan@wallentowitz.de>
	    Franck Jullien  <franck.jullien@gmail.com>
	    Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* gdb.texinfo: Add OpenRISC documentation.

gdb/ChangeLog:

2017-12-12  Stafford Horne  <shorne@gmail.com>
	    Stefan Wallentowitz  <stefan@wallentowitz.de>
	    Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
	    Franck Jullien  <franck.jullien@gmail.com>
	    Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* configure.tgt: Add targets for or1k and or1knd.
	* or1k-tdep.c: New file.
	* or1k-tdep.h: New file.
	* features/Makefile: Add or1k.xml to build.
	* features/or1k.xml: New file.
	* features/or1k-core.xml: New file.
	* features/or1k.c: Generated.

2 files changed, 54 insertions, 0 deletions

diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index 7710640..4e032ec 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,10 @@
+2017-12-12  Stafford Horne  <shorne@gmail.com>
+	    Stefan Wallentowitz  <stefan@wallentowitz.de>
+	    Franck Jullien  <franck.jullien@gmail.com>
+	    Jeremy Bennett  <jeremy.bennett@embecosm.com>
+
+	* gdb.texinfo: Add OpenRISC documentation.
+
 2017-12-08  Jan Kratochvil  <jan.kratochvil@redhat.com>
 
 	* gdb.texinfo (Index Files): Document .debug_names and -dwarf-5.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 062f01d..da3ed28 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -546,6 +546,11 @@ was developed by SRI International and the University of Cambridge
 Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
 ("CTSRD"), as part of the DARPA CRASH research programme.
 
+The original port to the OpenRISC 1000 is believed to be due to
+Alessandro Forin and Per Bothner.  More recent ports have been the work
+of Jeremy Bennett, Franck Jullien, Stefan Wallentowitz and
+Stafford Horne.
+
 @node Sample Session
 @chapter A Sample @value{GDBN} Session
 
@@ -22442,6 +22447,7 @@ acceptable commands.
 * M68K::                        Motorola M68K
 * MicroBlaze::			Xilinx MicroBlaze
 * MIPS Embedded::               MIPS Embedded
+* OpenRISC 1000::               OpenRISC 1000 (or1k)
 * PowerPC Embedded::            PowerPC Embedded
 * AVR::                         Atmel AVR
 * CRIS::                        CRIS
@@ -22651,6 +22657,38 @@ As usual, you can inquire about the @code{mipsfpu} variable with
 @samp{show mipsfpu}.
 @end table
 
+@node OpenRISC 1000
+@subsection OpenRISC 1000
+@cindex OpenRISC 1000
+
+@noindent
+The OpenRISC 1000 provides a free RISC instruction set architecture.  It is
+mainly provided as a soft-core which can run on Xilinx, Altera and other
+FPGA's.
+
+@value{GDBN} for OpenRISC supports the below commands when connecting to
+a target:
+
+@table @code
+
+@kindex target sim
+@item target sim
+
+Runs the builtin CPU simulator which can run very basic
+programs but does not support most hardware functions like MMU.
+For more complex use cases the user is advised to run an external
+target, and connect using @samp{target remote}.
+
+Example: @code{target sim}
+
+@item set debug or1k
+Toggle whether to display OpenRISC-specific debugging messages from the
+OpenRISC target support subsystem.
+
+@item show debug or1k
+Show whether OpenRISC-specific debugging messages are enabled.
+@end table
+
 @node PowerPC Embedded
 @subsection PowerPC Embedded
 
@@ -41739,6 +41777,7 @@ registers using the capitalization used in the description.
 * M68K Features::
 * NDS32 Features::
 * Nios II Features::
+* OpenRISC 1000 Features::
 * PowerPC Features::
 * S/390 and System z Features::
 * Sparc Features::
@@ -42025,6 +42064,14 @@ targets.  It should contain the 32 core registers (@samp{zero},
 @samp{pc}, and the 16 control registers (@samp{status} through
 @samp{mpuacc}).
 
+@node OpenRISC 1000 Features
+@subsection Openrisc 1000 Features
+@cindex target descriptions, OpenRISC 1000 features
+
+The @samp{org.gnu.gdb.or1k.group0} feature is required for OpenRISC 1000
+targets.  It should contain the 32 general purpose registers (@samp{r0}
+through @samp{r31}), @samp{ppc}, @samp{npc} and @samp{sr}.
+
 @node PowerPC Features
 @subsection PowerPC Features
 @cindex target descriptions, PowerPC features