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author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 14:53:08 +0800 |
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committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:31:25 +0800 |
commit | 86fbfedd715df8a89d73374d70b1f068f95b450e (patch) | |
tree | e569a7d8ff6b5cf8e154f295173d37a1772c4a27 /gdb/copying.awk | |
parent | da02021b59983145f7da0226afb46345cda5d9ef (diff) | |
download | gdb-86fbfedd715df8a89d73374d70b1f068f95b450e.zip gdb-86fbfedd715df8a89d73374d70b1f068f95b450e.tar.gz gdb-86fbfedd715df8a89d73374d70b1f068f95b450e.tar.bz2 |
RISC-V: Add T-Head VECTOR vendor extension.
T-Head has a range of vendor-specific instructions ([2]).
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the "XTheadVector" extension, a collection of
T-Head-specific vector instructions. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the RISC-V
toolchain conventions ([1]).
Here are some things that need to be explained:
The "XTheadVector" extension is not a custom-extension, but
a non-standard non-conforming extension. The encoding space
of the "TheadVector" instructions overlaps with those of
the 'V' extension. This encoding space conflict is not on
purpose, but the result of issues in the past that have
been resolved since. Therefore, the "XTheadVector" extension
and the 'V' extension are in conflict.
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
[2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): The
"XTheadVector" extension and the 'V' extension are in conflict.
(riscv_multi_subset_supports): Likewise..
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi:
* testsuite/gas/riscv/x-thead-vector-fail.d: New test.
* testsuite/gas/riscv/x-thead-vector-fail.l: New test.
* testsuite/gas/riscv/x-thead-vector.s: New test.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class):
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