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authorAndrew Cagney <cagney@redhat.com>2000-06-08 04:51:10 +0000
committerAndrew Cagney <cagney@redhat.com>2000-06-08 04:51:10 +0000
commitb0069a177563e97d76ab70c0e9f70ffe85759876 (patch)
tree790eec0e61715196f10d6e60d4394dc9ef045b8a /gdb/config/mips
parent1ba607adba3816e5352f639a27cffa20ee71813d (diff)
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Delete MIPS_DEFAULT_FPU from config/mips/*.h
Diffstat (limited to 'gdb/config/mips')
-rw-r--r--gdb/config/mips/tm-mips.h5
-rw-r--r--gdb/config/mips/tm-tx39.h2
-rw-r--r--gdb/config/mips/tm-tx39l.h2
-rw-r--r--gdb/config/mips/tm-vr4100.h1
-rw-r--r--gdb/config/mips/tm-vr4xxx.h1
-rw-r--r--gdb/config/mips/tm-vr4xxxel.h1
6 files changed, 2 insertions, 10 deletions
diff --git a/gdb/config/mips/tm-mips.h b/gdb/config/mips/tm-mips.h
index 4aa77f3..ff95113 100644
--- a/gdb/config/mips/tm-mips.h
+++ b/gdb/config/mips/tm-mips.h
@@ -129,11 +129,6 @@ extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
#define MIPS_REGSIZE 4
#endif
-/* The sizes of floating point registers. */
-
-#define MIPS_FPU_SINGLE_REGSIZE 4
-#define MIPS_FPU_DOUBLE_REGSIZE 8
-
/* Number of machine registers */
#ifndef NUM_REGS
diff --git a/gdb/config/mips/tm-tx39.h b/gdb/config/mips/tm-tx39.h
index 520db7b..c1d9cf7 100644
--- a/gdb/config/mips/tm-tx39.h
+++ b/gdb/config/mips/tm-tx39.h
@@ -17,8 +17,8 @@
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+#define GDB_MULTI_ARCH 1
#define MIPS_EABI 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
#include "mips/tm-bigmips.h"
diff --git a/gdb/config/mips/tm-tx39l.h b/gdb/config/mips/tm-tx39l.h
index 30ba78a..802e41b 100644
--- a/gdb/config/mips/tm-tx39l.h
+++ b/gdb/config/mips/tm-tx39l.h
@@ -17,8 +17,8 @@
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+#define GDB_MULTI_ARCH 1
#define MIPS_EABI 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
#include "mips/tm-mips.h"
diff --git a/gdb/config/mips/tm-vr4100.h b/gdb/config/mips/tm-vr4100.h
index 9c87619..faf0a96 100644
--- a/gdb/config/mips/tm-vr4100.h
+++ b/gdb/config/mips/tm-vr4100.h
@@ -18,7 +18,6 @@
Boston, MA 02111-1307, USA. */
#define MIPS_EABI 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
#define TARGET_PTR_BIT 64
#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-vr4xxx.h b/gdb/config/mips/tm-vr4xxx.h
index 2878227..7d2a78a 100644
--- a/gdb/config/mips/tm-vr4xxx.h
+++ b/gdb/config/mips/tm-vr4xxx.h
@@ -18,6 +18,5 @@
Boston, MA 02111-1307, USA. */
#define GDB_MULTI_ARCH 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-vr4xxxel.h b/gdb/config/mips/tm-vr4xxxel.h
index c9eedc3..1347af7 100644
--- a/gdb/config/mips/tm-vr4xxxel.h
+++ b/gdb/config/mips/tm-vr4xxxel.h
@@ -18,6 +18,5 @@
Boston, MA 02111-1307, USA. */
#define GDB_MULTI_ARCH 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
#include "mips/tm-mips64.h"