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authorRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:48:59 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:48:59 +0100
commit04a3379aceaeb8e29f2586d756d5f2ef26c85e7e (patch)
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parent1799c0d064f21e09666fd1ab19a31a957202f18b (diff)
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[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovable
SVE has single-bit floating-point constants that don't really have any relation to the AArch64 8-bit floating-point encoding. (E.g. one of the constants selects between 0 and 1.) The easiest way of representing them in the aarch64_opnd_info seemed to be to use the IEEE float representation directly, rather than invent some new scheme. This patch paves the way for that by making the code that converts IEEE doubles to IEEE floats accept any value in the range of an IEEE float, not just zero and 8-bit floats. It leaves the range checking to the caller (which already handles it). gas/ * config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename to... (can_convert_double_to_float): ...this. Accept any double-precision value that converts to single precision without loss of precision. (parse_aarch64_imm_float): Update accordingly.
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