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authorAndrew Burgess <andrew.burgess@embecosm.com>2017-11-09 20:59:13 +0000
committerAndrew Burgess <andrew.burgess@embecosm.com>2018-03-06 09:59:09 +0000
commitdbbb1059e62e9fed10b429c030f76f782cbc1fc4 (patch)
tree344ac48ce4ad6c3f4b4e1cfcd40cfc7ba571bf52 /gdb/MAINTAINERS
parent5dc4391345f6e86906a57af1434025cfb47b4100 (diff)
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gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
Diffstat (limited to 'gdb/MAINTAINERS')
-rw-r--r--gdb/MAINTAINERS5
1 files changed, 5 insertions, 0 deletions
diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS
index 8ff0d4a..79e6490 100644
--- a/gdb/MAINTAINERS
+++ b/gdb/MAINTAINERS
@@ -294,6 +294,11 @@ the native maintainer when resolving ABI issues.
powerpc --target=powerpc-eabi ,-Werror
+ riscv --target=riscv32-elf ,-Werror
+ --target=riscv64-elf ,-Werror
+ Andrew Burgess andrew.burgess@embecosm.com
+ Palmer Dabbelt palmer@sifive.com
+
rl78 --target=rl78-elf ,-Werror
rx --target=rx-elf ,-Werror