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| author | Walter Lee <walt@tilera.com> | 2013-02-19 16:22:42 +0000 |
|---|---|---|
| committer | Walter Lee <walt@tilera.com> | 2013-02-19 16:22:42 +0000 |
| commit | 3361b059eb46d2dfd9ed9119935faf3516c5e997 (patch) | |
| tree | d3d665d123c33c55aab5731cf685532aec82d437 /gdb/ChangeLog | |
| parent | bb1bcd865b70b25c093bc9069b75748e3cb46ae0 (diff) | |
| download | gdb-3361b059eb46d2dfd9ed9119935faf3516c5e997.zip gdb-3361b059eb46d2dfd9ed9119935faf3516c5e997.tar.gz gdb-3361b059eb46d2dfd9ed9119935faf3516c5e997.tar.bz2 | |
* tilegx-tdep.c (tilegx_analyze_prologue): add check for
for return address, "lr" register, saved on stack.
* tilegx-tdep.c (tilegx_frame_cache): update "PC" reg
after we invoke tilegx_analyze_prologue.
Diffstat (limited to 'gdb/ChangeLog')
| -rw-r--r-- | gdb/ChangeLog | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 47ae022..881379c 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,8 +1,15 @@ 2013-02-19 Jiong Wang <jiwang@tilera.com> + * tilegx-tdep.c (tilegx_analyze_prologue): add check for + for return address, "lr" register, saved on stack. + * tilegx-tdep.c (tilegx_frame_cache): update "PC" reg + after we invoke tilegx_analyze_prologue. + +2013-02-19 Jiong Wang <jiwang@tilera.com> + * tilegx-tdep.c (itilegx_gdbarch_init): char type should be signed. -2013-02-13 Jiong Wang <jiwang@tilera.com> +2013-02-19 Jiong Wang <jiwang@tilera.com> * tilegx-tdep.c (tilegx_skip_prologue): Use skip_prologue_using_sal. |