Fix spelling typos.

4 files changed, 39 insertions, 39 deletions

diff --git a/gas/testsuite/gas/arm/ldr-bad.l b/gas/testsuite/gas/arm/ldr-bad.l
index 554b4a3..6fc2071 100644
--- a/gas/testsuite/gas/arm/ldr-bad.l
+++ b/gas/testsuite/gas/arm/ldr-bad.l
@@ -1,7 +1,7 @@
 [^:]*: Assembler messages:
 [^:]*:5: Warning: destination register same as write-back base
-[^:]*:9: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]'
-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7'
+[^:]*:9: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]'
+[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7'
 [^:]*:15: Warning: destination register same as write-back base
 [^:]*:16: Error: cannot use register index with PC-relative addressing -- `ldr r2,\[r15,r2\]!'
 [^:]*:19: Error: cannot use register index with PC-relative addressing -- `ldr r1,\[r1,r15\]'
diff --git a/gas/testsuite/gas/arm/ldr-t-bad.l b/gas/testsuite/gas/arm/ldr-t-bad.l
index 95f420a..d83648b 100644
--- a/gas/testsuite/gas/arm/ldr-t-bad.l
+++ b/gas/testsuite/gas/arm/ldr-t-bad.l
@@ -1,9 +1,9 @@
 [^:]*: Assembler messages:
 [^:]*:8: Error: registers may not be the same -- `ldr r1,\[r1,#5\]!'
-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]'
+[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]'
 [^:]*:16: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,#4\]'
 [^:]*:25: Error: branch must be last instruction in IT block -- `ldrge r15,.0x4'
-[^:]*:30: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7'
+[^:]*:30: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7'
 [^:]*:36: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,r1\]'
 [^:]*:41: Error: r13 not allowed here -- `ldr r1,\[r2,r13\]'
 [^:]*:42: Error: r15 not allowed here -- `ldr r2,\[r2,r15\]'
diff --git a/gas/testsuite/gas/msp430/errata_warns.l b/gas/testsuite/gas/msp430/errata_warns.l
index 52df6b9..699274b 100644
--- a/gas/testsuite/gas/msp430/errata_warns.l
+++ b/gas/testsuite/gas/msp430/errata_warns.l
@@ -6,39 +6,39 @@
 [^:]*:13: Warning: CPU8: Stack pointer accessed with an odd offset
 [^:]*:14: Warning: CPU8: Stack pointer accessed with an odd offset
 [^:]*:15: Warning: CPU8: Stack pointer accessed with an odd offset
-[^:]*:18: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:19: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:20: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:21: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:21: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:22: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:23: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:24: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:25: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:26: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:30: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:31: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:31: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:34: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:34: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:35: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:36: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:37: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:38: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:39: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:40: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:41: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:42: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:43: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:44: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:45: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:46: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:47: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:48: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:49: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:50: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:51: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:52: Warning: CPU13: SR is destinstion of SR altering instruction
+[^:]*:18: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:19: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:20: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:21: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:21: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:22: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:23: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:24: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:25: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:26: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:30: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:31: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:31: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:34: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:34: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:35: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:36: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:37: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:38: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:39: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:40: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:41: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:42: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:43: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:44: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:45: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:46: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:47: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:48: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:49: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:50: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:51: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:52: Warning: CPU13: SR is destination of SR altering instruction
 [^:]*:56: Warning: CPU19: Instruction setting CPUOFF must be followed by a NOP
 [^:]*:57: Warning: CPU19: Instruction setting CPUOFF must be followed by a NOP
-[^:]*:57: Warning: CPU13: SR is destinstion of SR altering instruction
+[^:]*:57: Warning: CPU13: SR is destination of SR altering instruction
diff --git a/gas/testsuite/gas/tic54x/opcodes.s b/gas/testsuite/gas/tic54x/opcodes.s
index 3e1e84b..99b358d 100644
--- a/gas/testsuite/gas/tic54x/opcodes.s
+++ b/gas/testsuite/gas/tic54x/opcodes.s
@@ -119,7 +119,7 @@ _opcodes:
 	ld	#7,arp		

 	ld	*ar2+,asm	

 	ldm	ar3,a		

-	ld	*ar2+,a || mac	*ar3+,b	; single-line parallell

+	ld	*ar2+,a || mac	*ar3+,b	; single-line parallel

 	ld	*ar4+,b	|| macr	*ar5+,a	; with optional DST_ specified

 	ld	*ar2+,a			; double-line parallel

 	|| mas	*ar3+