oWed Jul 31 15:41:42 1996 James G. Smith <jsmith@cygnus.co.uk>

	* config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
 	pre-cursor to adding Thumb support. Also added cpu_variant flag
 	information to each of the asm_flg structures.
	(md_parse_option): Updated ARM7 parsing to allow 't' for
 	thumb/halfword support, aswell as 'm' for long multiply.
	(md_show_usage): Updated help message.
	(md_assemble): Check that instruction flags are applicated to the
 	current cpu variant.
	(md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
 	BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
 	signextension instructions.
	(do_ldst): Generate halfword and signextension variants if
 	mnemonic flags match.
	(ldst_extend): Do not allow shifts in the offset field of halfword
 	or signextension instructions.
	(validate_offset_imm): Provide check on halfword and signextension
 	immediate range.
	(add_to_lit_pool): Merge identical literal pool values.

Wed Jul 31 15:55:12 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* gas/arm/arm7t.s: Added.
	* gas/arm/arm7t.d: Added.
	* gas/arm/arm.exp: Updated to run the new test.

3 files changed, 86 insertions, 0 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 95884fd..a47fbfe 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+Wed Jul 31 15:55:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
+
+	* gas/arm/arm7t.s: Added.
+	* gas/arm/arm7t.d: Added.
+	* gas/arm/arm.exp: Updated to run the new test.
+
 Mon Jul  8 14:27:39 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* gas/m68k/pcrel.d: Rename from schwab.d.
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index 339c3e6..91b698f 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -10,7 +10,19 @@ if [istarget arm-*-*] then {
 
     gas_test "arm7dm.s" "" $stdoptlist "Arm 7DM instructions"
 
+    run_dump_test "arm7t"
+
     gas_test "copro.s" "" $stdoptlist "Co processor instructions"
 
     gas_test "float.s" "" $stdoptlist "Core floating point instructions"
 }
+
+# Not all arm targets are bi-endian, so only run this test on ones
+# we know that are.  FIXME: We should probably also key off armeb/armel.
+
+if [istarget arm-*-pe] {
+    run_dump_test "le-fpconst"
+
+    # Since big-endian numbers have the normal format, this doesn't exist.
+    #run_dump_test "be-fpconst"
+}
diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d
new file mode 100644
index 0000000..8bc5c17
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm7t.d
@@ -0,0 +1,68 @@
+#objdump: -dr
+#name: ARM arm7t
+#as: -marm7t
+
+# Test the halfword and signextend memory transfers:
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+00000000 <[^>]*> e1d100b0	ldrh	r0, \[r1\]
+00000004 <[^>]*> e1f100b0	ldrh	r0, \[r1\]!
+00000008 <[^>]*> e19100b2	ldrh	r0, \[r1, r2\]
+0000000c <[^>]*> e1b100b2	ldrh	r0, \[r1, r2\]!
+00000010 <[^>]*> e1d100bc	ldrh	r0, \[r1, #c\]
+00000014 <[^>]*> e1f100bc	ldrh	r0, \[r1, #c\]!
+00000018 <[^>]*> e15100bc	ldrh	r0, \[r1, -#c\]
+0000001c <[^>]*> e09100b2	ldrh	r0, \[r1\], r2
+00000020 <[^>]*> e3a00cff	mov	r0, #ff00
+00000024 <[^>]*> e1df0bb4	ldrh	r0, 000000e0 <\$\$lit_1>
+00000028 <[^>]*> e1df0abc	ldrh	r0, 000000dc <.L2>
+0000002c <[^>]*> e1c100b0	strh	r0, \[r1\]
+00000030 <[^>]*> e1e100b0	strh	r0, \[r1\]!
+00000034 <[^>]*> e18100b2	strh	r0, \[r1, r2\]
+00000038 <[^>]*> e1a100b2	strh	r0, \[r1, r2\]!
+0000003c <[^>]*> e1c100bc	strh	r0, \[r1, #c\]
+00000040 <[^>]*> e1e100bc	strh	r0, \[r1, #c\]!
+00000044 <[^>]*> e14100bc	strh	r0, \[r1, -#c\]
+00000048 <[^>]*> e08100b2	strh	r0, \[r1\], r2
+0000004c <[^>]*> e1cf08b8	strh	r0, 000000dc <.L2>
+00000050 <[^>]*> e1d100d0	ldrsb	r0, \[r1\]
+00000054 <[^>]*> e1f100d0	ldrsb	r0, \[r1\]!
+00000058 <[^>]*> e19100d2	ldrsb	r0, \[r1, r2\]
+0000005c <[^>]*> e1b100d2	ldrsb	r0, \[r1, r2\]!
+00000060 <[^>]*> e1d100dc	ldrsb	r0, \[r1, #c\]
+00000064 <[^>]*> e1f100dc	ldrsb	r0, \[r1, #c\]!
+00000068 <[^>]*> e15100dc	ldrsb	r0, \[r1, -#c\]
+0000006c <[^>]*> e09100d2	ldrsb	r0, \[r1\], r2
+00000070 <[^>]*> e3a000de	mov	r0, #de
+00000074 <[^>]*> e1df06d0	ldrsb	r0, 000000dc <.L2>
+00000078 <[^>]*> e1d100f0	ldrsh	r0, \[r1\]
+0000007c <[^>]*> e1f100f0	ldrsh	r0, \[r1\]!
+00000080 <[^>]*> e19100f2	ldrsh	r0, \[r1, r2\]
+00000084 <[^>]*> e1b100f2	ldrsh	r0, \[r1, r2\]!
+00000088 <[^>]*> e1d100fc	ldrsh	r0, \[r1, #c\]
+0000008c <[^>]*> e1f100fc	ldrsh	r0, \[r1, #c\]!
+00000090 <[^>]*> e15100fc	ldrsh	r0, \[r1, -#c\]
+00000094 <[^>]*> e09100f2	ldrsh	r0, \[r1\], r2
+00000098 <[^>]*> e3a00cff	mov	r0, #ff00
+0000009c <[^>]*> e1df03fc	ldrsh	r0, 000000e0 <\$\$lit_1>
+000000a0 <[^>]*> e1df03f4	ldrsh	r0, 000000dc <.L2>
+000000a4 <[^>]*> e19100b2	ldrh	r0, \[r1, r2\]
+000000a8 <[^>]*> 119100b2	ldrneh	r0, \[r1, r2\]
+000000ac <[^>]*> 819100b2	ldrhih	r0, \[r1, r2\]
+000000b0 <[^>]*> b19100b2	ldrlth	r0, \[r1, r2\]
+000000b4 <[^>]*> e19100f2	ldrsh	r0, \[r1, r2\]
+000000b8 <[^>]*> 119100f2	ldrnesh	r0, \[r1, r2\]
+000000bc <[^>]*> 819100f2	ldrhish	r0, \[r1, r2\]
+000000c0 <[^>]*> b19100f2	ldrltsh	r0, \[r1, r2\]
+000000c4 <[^>]*> e19100d2	ldrsb	r0, \[r1, r2\]
+000000c8 <[^>]*> 119100d2	ldrnesb	r0, \[r1, r2\]
+000000cc <[^>]*> 819100d2	ldrhisb	r0, \[r1, r2\]
+000000d0 <[^>]*> b19100d2	ldrltsb	r0, \[r1, r2\]
+000000d4 <[^>]*> e1df00f4	ldrsh	r0, 000000e0 <\$\$lit_1>
+000000d8 <[^>]*> e1df00f4	ldrsh	r0, 000000e4 <\$\$lit_1\+4>
+...
+[		]*RELOC: 000000dc 32 .LC0
+000000e0 <[^>]*> 0000c0de	.*
+000000e4 <[^>]*> 0000dead	.*