x86: handle immediate operands for .insn

Since we have no insn suffix and it's also not realistic to infer
immediate size from the size of other (typically register) operands
(like optimize_imm() does), and since we also don't have a template
telling us permitted size(s), a new syntax construct is introduced to
allow size (and signedness) specification. In the absence of such, the
size is inferred from significant bits (which obviously may yield
inconsistent results at least for effectively negative values, depending
on whether BFD64 is enabled), and only if supplied expressions can be
evaluated at parsing time. Being explicit is generally recommended to
users.

Size specification is permitted at bit granularity, but of course the
eventually emitted immediate values will be padded up to 8-, 16-, 32-,
or 64-bit fields.

4 files changed, 74 insertions, 1 deletions

diff --git a/gas/testsuite/gas/i386/insn-32.d b/gas/testsuite/gas/i386/insn-32.d
index d898a71..c2d8202 100644
--- a/gas/testsuite/gas/i386/insn-32.d
+++ b/gas/testsuite/gas/i386/insn-32.d
@@ -1,5 +1,7 @@
+#as: --divide
 #objdump: -dw
 #name: .insn (32-bit code)
+#xfail: *-*-darwin*
 
 .*: +file format .*
 
@@ -10,6 +12,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 90[ 	]+pause
 [ 	]*[a-f0-9]+:	f3 90[ 	]+pause
 [ 	]*[a-f0-9]+:	d9 ee[ 	]+fldz
+[ 	]*[a-f0-9]+:	d9 ee[ 	]+fldz
 [ 	]*[a-f0-9]+:	f3 0f 01 e8[ 	]+setssbsy
 [ 	]*[a-f0-9]+:	8b c1[ 	]+mov    %ecx,%eax
 [ 	]*[a-f0-9]+:	66 8b c8[ 	]+mov    %ax,%cx
@@ -17,7 +20,10 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	8b 0c 05 44 44 00 00[ 	]+mov    0x4444\(,%eax,1\),%ecx
 [ 	]*[a-f0-9]+:	66 0f b6 cc[ 	]+movzbw %ah,%cx
 [ 	]*[a-f0-9]+:	0f b7 c8[ 	]+movzwl %ax,%ecx
+[ 	]*[a-f0-9]+:	64 f0 80 30 01[ 	]+lock xorb \$(0x)?1,%fs:\(%eax\)
 [ 	]*[a-f0-9]+:	0f ca[ 	]+bswap  %edx
+[ 	]*[a-f0-9]+:	c7 f8 02 00 00 00[ 	]+xbegin [0-9a-f]+ <insn\+.*>
+[ 	]*[a-f0-9]+:	e2 f8[ 	]+loop   [0-9a-f]+ <insn\+.*>
 [ 	]*[a-f0-9]+:	c5 fc 77[ 	]+vzeroall
 [ 	]*[a-f0-9]+:	c4 e1 7c 77[ 	]+vzeroall
 [ 	]*[a-f0-9]+:	c5 f1 58 d0[ 	]+vaddpd %xmm0,%xmm1,%xmm2
@@ -27,6 +33,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c4 e3 69 68 19 00[ 	]+vfmaddps %xmm0,\(%ecx\),%xmm2,%xmm3
 [ 	]*[a-f0-9]+:	c4 e3 e9 68 19 00[ 	]+vfmaddps \(%ecx\),%xmm0,%xmm2,%xmm3
 [ 	]*[a-f0-9]+:	c4 e3 e9 68 18 10[ 	]+vfmaddps \(%eax\),%xmm1,%xmm2,%xmm3
+[ 	]*[a-f0-9]+:	c4 e3 69 48 19 00[ 	]+vpermil2ps \$(0x)?0,%xmm0,\(%ecx\),%xmm2,%xmm3
+[ 	]*[a-f0-9]+:	c4 e3 e9 48 19 02[ 	]+vpermil2ps \$(0x)?2,\(%ecx\),%xmm0,%xmm2,%xmm3
+[ 	]*[a-f0-9]+:	c4 e3 e9 48 18 13[ 	]+vpermil2ps \$(0x)?3,\(%eax\),%xmm1,%xmm2,%xmm3
 [ 	]*[a-f0-9]+:	c5 f8 92 c8[ 	]+kmovw  %eax,%k1
 [ 	]*[a-f0-9]+:	c5 f8 93 c1[ 	]+kmovw  %k1,%eax
 [ 	]*[a-f0-9]+:	62 f1 74 18 58 d0[ 	]+vaddps \{rn-sae\},%zmm0,%zmm1,%zmm2
@@ -41,4 +50,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 f5 fd 58 5a 40 01[ 	]+vcvtpd2ph (0x)?8\(%eax\)\{1to8\},%xmm0
 [ 	]*[a-f0-9]+:	62 f5 7c 48 5a 40 01[ 	]+vcvtph2pd 0x10\(%eax\),%zmm0
 [ 	]*[a-f0-9]+:	62 f5 7c 58 5a 40 01[ 	]+vcvtph2pd (0x)?2\(%eax\)\{1to8\},%zmm0
+[ 	]*[a-f0-9]+:	62 f3 7d 28 66 40 01 ff[ 	]+vfpclasspsy \$0xff,0x20\(%eax\),%k0
+[ 	]*[a-f0-9]+:	62 f3 7d 28 66 40 01 ff[ 	]+vfpclasspsy \$0xff,0x20\(%eax\),%k0
+[ 	]*[a-f0-9]+:	62 f3 7d 38 66 40 01 ff[ 	]+vfpclassps \$0xff,(0x)?4\(%eax\)\{1to8\},%k0
+[ 	]*[a-f0-9]+:	62 f3 7d 38 66 40 01 ff[ 	]+vfpclassps \$0xff,(0x)?4\(%eax\)\{1to8\},%k0
 #pass
diff --git a/gas/testsuite/gas/i386/insn-32.s b/gas/testsuite/gas/i386/insn-32.s
index d54ad3b..20bae32 100644
--- a/gas/testsuite/gas/i386/insn-32.s
+++ b/gas/testsuite/gas/i386/insn-32.s
@@ -9,6 +9,7 @@ insn:
 
 	# fldz
 	.insn 0xd9ee
+	.insn 0xd9, $0xee
 
 	# setssbsy
 	.insn 0xf30f01e8
@@ -23,9 +24,20 @@ insn:
 	.insn 0x0fb6, %ah, %cx
 	.insn 0x0fb7, %eax, %ecx
 
+	# xorb
+	.insn lock 0x80/6, $1, %fs:(%eax)
+
 	# bswap
 	.insn 0x0fc8+r, %edx
 
+1:
+	# xbegin 3f
+	.insn 0xc7f8, $3f-2f{:s32}
+2:
+	# loop 1b
+	.insn 0xe2, $1b-3f{:s8}
+3:
+
 	# vzeroall
 	.insn VEX.256.0F.WIG 0x77
 	.insn {vex3} VEX.L1 0x0f77
@@ -43,6 +55,11 @@ insn:
 	.insn VEX.66.0F3A.W1 0x68, %xmm0, (%ecx), %xmm2, %xmm3
 	.insn VEX.66.0F3A.W1 0x68, (%eax), %xmm1, %xmm2, %xmm3
 
+	# vpermil2ps
+	.insn VEX.66.0F3A.W0 0x48, $0, %xmm0, (%ecx), %xmm2, %xmm3
+	.insn VEX.66.0F3A.W1 0x48, $2, %xmm0, (%ecx), %xmm2, %xmm3
+	.insn VEX.66.0F3A.W1 0x48, $3, (%eax), %xmm1, %xmm2, %xmm3
+
 	# kmovw
 	.insn VEX.L0.0F.W0 0x92, %eax, %k1
 	.insn VEX.L0.0F.W0 0x93, %k1, %eax
@@ -68,3 +85,10 @@ insn:
 	# vcvtph2pd
 	.insn EVEX.M5.W0 0x5a, 16(%eax){:d16}, %zmm0
 	.insn EVEX.M5.W0 0x5a, 2(%eax){1to8:d2}, %zmm0
+
+	.intel_syntax noprefix
+	# vfpclassps
+	.insn EVEX.256.66.0f3a.W0 0x66, k0, [eax+32], 0xff
+	.insn EVEX.66.0f3a.W0 0x66, k0, ymmword ptr [eax+32], 0xff
+	.insn EVEX.256.66.0f3a.W0 0x66, k0, [eax+4]{1to8}, 0xff
+	.insn EVEX.66.0f3a.W0 0x66, k0, dword ptr [eax+4]{1to8}, 0xff
diff --git a/gas/testsuite/gas/i386/insn-64.d b/gas/testsuite/gas/i386/insn-64.d
index 0f1ec88..0c1f0c5 100644
--- a/gas/testsuite/gas/i386/insn-64.d
+++ b/gas/testsuite/gas/i386/insn-64.d
@@ -1,5 +1,7 @@
-#objdump: -dw
+#as: --divide
+#objdump: -dwr
 #name: .insn (64-bit code)
+#xfail: *-*-darwin*
 
 .*: +file format .*
 
@@ -18,8 +20,14 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f be cc[ 	]+movsbw %ah,%cx
 [ 	]*[a-f0-9]+:	0f bf c8[ 	]+movswl %ax,%ecx
 [ 	]*[a-f0-9]+:	48 63 c8[ 	]+movslq %eax,%rcx
+[ 	]*[a-f0-9]+:	f0 80 35 ((00|ff) ){4}01[ 	]+lock xorb \$(0x)?1,[-x01]+\(%rip\) *# .*: (R_X86_64_PC32	lock-(0x)?5|IMAGE_REL_AMD64_REL32	lock)
 [ 	]*[a-f0-9]+:	48 0f ca[ 	]+bswap  %rdx
 [ 	]*[a-f0-9]+:	41 0f c8[ 	]+bswap  %r8d
+[ 	]*[a-f0-9]+:	c7 f8 02 00 00 00[ 	]+xbegin [0-9a-f]+ <insn\+.*>
+[ 	]*[a-f0-9]+:	e2 f8[ 	]+loop   [0-9a-f]+ <insn\+.*>
+[ 	]*[a-f0-9]+:	05 00 00 00 00[ 	]+add    \$(0x)?0,%eax	.*: (R_X86_64_32|IMAGE_REL_AMD64_ADDR32)	var
+[ 	]*[a-f0-9]+:	48 05 00 00 00 00[ 	]+add    \$(0x)?0,%rax	.*: R_X86_64_32S	var
+[ 	]*[a-f0-9]+:	81 3d (00|fc) ((00|ff) ){3}13 12 23 21[ 	]+cmpl   \$0x21231213,[-x04]+\(%rip\) *# .*: (R_X86_64_PC32	var-(0x)?8|IMAGE_REL_AMD64_REL32	var)
 [ 	]*[a-f0-9]+:	c5 fc 77[ 	]+vzeroall
 [ 	]*[a-f0-9]+:	c4 e1 7c 77[ 	]+vzeroall
 [ 	]*[a-f0-9]+:	c4 c1 71 58 d0[ 	]+vaddpd %xmm8,%xmm1,%xmm2
@@ -29,6 +37,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c4 e3 69 68 19 80[ 	]+vfmaddps %xmm8,\(%rcx\),%xmm2,%xmm3
 [ 	]*[a-f0-9]+:	67 c4 e3 e9 68 19 00[ 	]+vfmaddps \(%ecx\),%xmm0,%xmm2,%xmm3
 [ 	]*[a-f0-9]+:	c4 c3 e9 68 18 10[ 	]+vfmaddps \(%r8\),%xmm1,%xmm2,%xmm3
+[ 	]*[a-f0-9]+:	c4 e3 69 48 19 80[ 	]+vpermil2ps \$(0x)0,%xmm8,\(%rcx\),%xmm2,%xmm3
+[ 	]*[a-f0-9]+:	67 c4 e3 e9 48 19 02[ 	]+vpermil2ps \$(0x)2,\(%ecx\),%xmm0,%xmm2,%xmm3
+[ 	]*[a-f0-9]+:	c4 c3 e9 48 18 13[ 	]+vpermil2ps \$(0x)3,\(%r8\),%xmm1,%xmm2,%xmm3
 [ 	]*[a-f0-9]+:	c4 c1 78 92 c8[ 	]+kmovw  %r8d,%k1
 [ 	]*[a-f0-9]+:	c5 78 93 c1[ 	]+kmovw  %k1,%r8d
 [ 	]*[a-f0-9]+:	62 b1 74 38 58 d0[ 	]+vaddps \{rd-sae\},%zmm16,%zmm1,%zmm2
diff --git a/gas/testsuite/gas/i386/insn-64.s b/gas/testsuite/gas/i386/insn-64.s
index 9dfdd3a..3152ec9 100644
--- a/gas/testsuite/gas/i386/insn-64.s
+++ b/gas/testsuite/gas/i386/insn-64.s
@@ -24,10 +24,30 @@ insn:
 	.insn 0x0fbf, %eax, %ecx
 	.insn 0x63, %rax, %rcx
 
+	# xorb
+	.insn lock 0x80/6, $1, lock(%rip)
+
 	# bswap
 	.insn 0x0fc8+r, %rdx
 	.insn 0x0fc8+r, %r8d
 
+1:
+	# xbegin 3f
+	.insn 0xc7f8, $3f-2f{:s32}
+2:
+	# loop 1b
+	.insn 0xe2, $1b-3f{:s8}
+3:
+
+	# add $var, %eax
+	.insn 0x05, $var{:u32}
+
+	# add $var, %rax
+	.insn rex.w 0x05, $var{:s32}
+
+	# cmpl (32-bit immediate split into two 16-bit halves)
+	.insn 0x81/7, $0x1213, $0x2123, var(%rip)
+
 	# vzeroall
 	.insn VEX.256.0F.WIG 0x77
 	.insn {vex3} VEX.L1 0x0f77
@@ -45,6 +65,11 @@ insn:
 	.insn VEX.66.0F3A.W1 0x68, %xmm0, (%ecx), %xmm2, %xmm3
 	.insn VEX.66.0F3A.W1 0x68, (%r8), %xmm1, %xmm2, %xmm3
 
+	# vpermil2ps
+	.insn VEX.66.0F3A.W0 0x48, $0, %xmm8, (%rcx), %xmm2, %xmm3
+	.insn VEX.66.0F3A.W1 0x48, $2, %xmm0, (%ecx), %xmm2, %xmm3
+	.insn VEX.66.0F3A.W1 0x48, $3, (%r8), %xmm1, %xmm2, %xmm3
+
 	# kmovw
 	.insn VEX.L0.0F.W0 0x92, %r8d, %k1
 	.insn VEX.L0.0F.W0 0x93, %k1, %r8d