Add support for the M32R2 processor.

4 files changed, 229 insertions, 0 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d3de7c4..80243a4 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2003-12-02  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* gas/m32r/m32r2.exp: New file for m32r2.
+	* gas/m32r/m32r2.s: Likewise.
+	* gas/m32r/m32r2.d: Likewise.
+
 2003-12-03  Nick Clifton  <nickc@redhat.com>
 
 	* gas/vax/vax.exp (do_quad): Treat a vax-*-linux-gnu target as an
diff --git a/gas/testsuite/gas/m32r/m32r2.d b/gas/testsuite/gas/m32r/m32r2.d
new file mode 100644
index 0000000..a17ed0f
--- /dev/null
+++ b/gas/testsuite/gas/m32r/m32r2.d
@@ -0,0 +1,92 @@
+#as: -m32r2
+#objdump: -dr
+#name: m32r2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0000 <setpsw>:
+   0:	71 c1 71 ff 	setpsw #0xc1 -> setpsw #0xff
+
+0+0004 <clrpsw>:
+   4:	72 c1 72 ff 	clrpsw #0xc1 -> clrpsw #0xff
+
+0+0008 <bset>:
+   8:	a0 61 00 04 	bset #0x0,@\(4,r1\)
+   c:	a1 61 00 04 	bset #0x1,@\(4,r1\)
+  10:	a7 61 00 04 	bset #0x7,@\(4,r1\)
+
+0+0014 <bclr>:
+  14:	a0 71 00 04 	bclr #0x0,@\(4,r1\)
+  18:	a1 71 00 04 	bclr #0x1,@\(4,r1\)
+  1c:	a7 71 00 04 	bclr #0x7,@\(4,r1\)
+
+0+0020 <btst>:
+  20:	00 fd 01 fd 	btst #0x0,fp -> btst #0x1,fp
+  24:	07 fd f0 00 	btst #0x7,fp \|\| nop
+  28:	01 fd 90 82 	btst #0x1,fp \|\| mv r0,r2
+  2c:	01 fd 90 82 	btst #0x1,fp \|\| mv r0,r2
+
+0+0030 <divuh>:
+  30:	9d 1d 00 10 	divuh fp,fp
+
+0+0034 <divb>:
+  34:	9d 0d 00 18 	divb fp,fp
+
+0+0038 <divub>:
+  38:	9d 1d 00 18 	divub fp,fp
+
+0+003c <remh>:
+  3c:	9d 2d 00 10 	remh fp,fp
+
+0+0040 <remuh>:
+  40:	9d 3d 00 10 	remuh fp,fp
+
+0+0044 <remb>:
+  44:	9d 2d 00 18 	remb fp,fp
+
+0+0048 <remub>:
+  48:	9d 3d 00 18 	remub fp,fp
+
+0+004c <sll>:
+  4c:	10 41 92 43 	sll r0,r1 \|\| sll r2,r3
+  50:	12 43 90 61 	sll r2,r3 \|\| mul r0,r1
+  54:	10 41 92 63 	sll r0,r1 \|\| mul r2,r3
+  58:	60 01 92 43 	ldi r0,#1 \|\| sll r2,r3
+  5c:	10 41 e2 01 	sll r0,r1 \|\| ldi r2,#1
+
+0+0060 <slli>:
+  60:	50 41 d2 5f 	slli r0,#0x1 \|\| slli r2,#0x1f
+  64:	52 5f 90 61 	slli r2,#0x1f \|\| mul r0,r1
+  68:	50 41 92 63 	slli r0,#0x1 \|\| mul r2,r3
+  6c:	60 01 d2 5f 	ldi r0,#1 \|\| slli r2,#0x1f
+  70:	50 41 e2 01 	slli r0,#0x1 \|\| ldi r2,#1
+
+0+0074 <sra>:
+  74:	10 21 92 23 	sra r0,r1 \|\| sra r2,r3
+  78:	12 23 90 61 	sra r2,r3 \|\| mul r0,r1
+  7c:	10 21 92 63 	sra r0,r1 \|\| mul r2,r3
+  80:	60 01 92 23 	ldi r0,#1 \|\| sra r2,r3
+  84:	10 21 e2 01 	sra r0,r1 \|\| ldi r2,#1
+
+0+0088 <srai>:
+  88:	50 21 d2 3f 	srai r0,#0x1 \|\| srai r2,#0x1f
+  8c:	52 3f 90 61 	srai r2,#0x1f \|\| mul r0,r1
+  90:	50 21 92 63 	srai r0,#0x1 \|\| mul r2,r3
+  94:	60 01 d2 3f 	ldi r0,#1 \|\| srai r2,#0x1f
+  98:	50 21 e2 01 	srai r0,#0x1 \|\| ldi r2,#1
+
+0+009c <srl>:
+  9c:	10 01 92 03 	srl r0,r1 \|\| srl r2,r3
+  a0:	12 03 90 61 	srl r2,r3 \|\| mul r0,r1
+  a4:	10 01 92 63 	srl r0,r1 \|\| mul r2,r3
+  a8:	60 01 92 03 	ldi r0,#1 \|\| srl r2,r3
+  ac:	10 01 e2 01 	srl r0,r1 \|\| ldi r2,#1
+
+0+00b0 <srli>:
+  b0:	50 01 d2 1f 	srli r0,#0x1 \|\| srli r2,#0x1f
+  b4:	52 1f 90 61 	srli r2,#0x1f \|\| mul r0,r1
+  b8:	50 01 92 63 	srli r0,#0x1 \|\| mul r2,r3
+  bc:	60 01 d2 1f 	ldi r0,#1 \|\| srli r2,#0x1f
+  c0:	50 01 e2 01 	srli r0,#0x1 \|\| ldi r2,#1
diff --git a/gas/testsuite/gas/m32r/m32r2.exp b/gas/testsuite/gas/m32r/m32r2.exp
new file mode 100644
index 0000000..03a160a
--- /dev/null
+++ b/gas/testsuite/gas/m32r/m32r2.exp
@@ -0,0 +1,5 @@
+# M32R2 assembler testsuite.
+
+if [istarget m32r*-*-*] {
+    run_dump_test "m32r2"
+}
diff --git a/gas/testsuite/gas/m32r/m32r2.s b/gas/testsuite/gas/m32r/m32r2.s
new file mode 100644
index 0000000..4f753c0
--- /dev/null
+++ b/gas/testsuite/gas/m32r/m32r2.s
@@ -0,0 +1,126 @@
+# Test new instructions
+	
+	.text
+	.global setpsw
+setpsw:
+	setpsw 0xc1
+	setpsw 0xff
+
+	.text
+	.global clrpsw
+clrpsw:
+	clrpsw 0xc1
+	clrpsw 0xff
+
+	.text
+	.global bset
+bset:
+	bset #0,@(4,r1)
+	bset #1,@(4,r1)
+	bset #7,@(4,r1)
+
+	.text
+	.global bclr
+bclr:
+	bclr #0,@(4,r1)
+	bclr #1,@(4,r1)
+	bclr #7,@(4,r1)
+
+	.text
+	.global btst
+btst:
+	btst #0,fp
+	btst #1,fp
+	btst #7,fp
+	btst #1,fp || mv r0,r2
+	mv r0,r2 || btst #1,fp
+
+	.text
+	.global divuh
+divuh:
+	divuh fp,fp
+
+	.text
+	.global divb
+divb:
+	divb fp,fp
+	
+	.text
+	.global divub
+divub:
+	divub fp,fp
+	
+	.text
+	.global remh
+remh:
+	remh fp,fp
+	
+	.text
+	.global remuh
+remuh:
+	remuh fp,fp
+	
+	.text
+	.global remb
+remb:
+	remb fp,fp
+	
+	.text
+	.global remub
+remub:
+	remub fp,fp
+	
+	.text
+	.global sll
+sll:
+	sll r0,r1 || sll r2,r3
+	mul r0,r1 || sll r2,r3
+	sll r0,r1 || mul r2,r3
+	ldi r0,#1 || sll r2,r3
+	sll r0,r1 || ldi r2,#1
+
+	.text
+	.global slli
+slli:
+	slli r0,#1 || slli r2,#31
+	mul r0,r1 || slli r2,#31
+	slli r0,#1 || mul r2,r3
+	ldi r0,#1 || slli r2,#31
+	slli r0,#1 || ldi r2,#1
+
+	.text
+	.global sra
+sra:
+	sra r0,r1 || sra r2,r3
+	mul r0,r1 || sra r2,r3
+	sra r0,r1 || mul r2,r3
+	ldi r0,#1 || sra r2,r3
+	sra r0,r1 || ldi r2,#1
+
+	.text
+	.global srai
+srai:
+	srai r0,#1 || srai r2,#31
+	mul r0,r1 || srai r2,#31
+	srai r0,#1 || mul r2,r3
+	ldi r0,#1 || srai r2,#31
+	srai r0,#1 || ldi r2,#1
+
+	.text
+	.global sra
+srl:
+	srl r0,r1 || srl r2,r3
+	mul r0,r1 || srl r2,r3
+	srl r0,r1 || mul r2,r3
+	ldi r0,#1 || srl r2,r3
+	srl r0,r1 || ldi r2,#1
+
+	.text
+	.global srai
+srli:
+	srli r0,#1 || srli r2,#31
+	mul r0,r1 || srli r2,#31
+	srli r0,#1 || mul r2,r3
+	ldi r0,#1 || srli r2,#31
+	srli r0,#1 || ldi r2,#1
+