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author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-11-18 07:47:42 +0000 |
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committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-11-28 01:03:18 +0000 |
commit | 634001bb4bbeb44431749dde5140b34e24b7a641 (patch) | |
tree | f051d5d22a6a0566275582e8fa91f3563a23a935 /gas/testsuite | |
parent | 97f006bc56afa41b3c5d4c4b0d0936aaf83b15d5 (diff) | |
download | gdb-634001bb4bbeb44431749dde5140b34e24b7a641.zip gdb-634001bb4bbeb44431749dde5140b34e24b7a641.tar.gz gdb-634001bb4bbeb44431749dde5140b34e24b7a641.tar.bz2 |
RISC-V: Better support for long instructions (assembler)
Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit
instructions with .insn") tried to start supporting long instructions but
it was insufficient.
1. It heavily depended on the bignum internals (radix of 2^16),
2. It generates "value conflicts with instruction length" even if a big
number instruction encoding does not exceed its expected length and
3. Because long opcode was handled separately (from struct riscv_cl_insn),
some information like DWARF line number correspondence was missing.
To resolve these problems, this commit:
1. Handles bignum (and its encodings) precisely and
2. Incorporates long opcode handling into regular instruction handling.
This commit will be tested on the separate commit.
gas/ChangeLog:
* config/tc-riscv.c (struct riscv_cl_insn): Add long opcode field.
(create_insn) Clear long opcode marker.
(install_insn) Install longer opcode as well.
(s_riscv_insn) Likewise.
(riscv_ip_hardcode): Make big number handling stricter. Length and
the value conflicts only if the bignum size exceeds the expected
maximum length.
Diffstat (limited to 'gas/testsuite')
0 files changed, 0 insertions, 0 deletions