gas:

	* config/tc-arm.c (T_OPCODE_BRANCH, encode_arm_addr_mode_2)
	(encode_arm_addr_mode_3, encode_arm_cp_address, do_blx, do_t_blx)
	(do_t_branch, insns [b, bl]): Don't encode pipeline offset.
	(s_arm_elf_cons): Disallow use of (plt) suffix.
	(do_adrl): Adjust X_add_number unconditionally.
	(md_pcrel_from): Rename md_pcrel_from_section, add second segT
	argument.  Handle all adjustment for pipeline offset here.
	(md_apply_fix): No need to undo work of md_pcrel_from.  No
	need to extract pre-encoded pipeline adjustments from various
	branch instructions.  Generally, assume instructions are already
	all-bits-zero in the field being fixed up.  Remove all OBJ_ELF
	special cases.  Handle BFD_RELOC_ARM_PLT32 like
	BFD_RELOC_ARM_PCREL_BRANCH.
	(tc_gen_reloc): Remove OBJ_ELF special case.
	* config/tc-arm.c: Define MD_PCREL_FROM_SECTION.

gas/testsuite:
	* gas/arm/arm.exp: Don't special case ldconst, arm7t, or copro
	for *-wince-*.
	* gas/arm/wince_arm7t.d, gas/arm/wince_copro.d
	* gas/arm/wince_ldconst.d: Delete.

6 files changed, 11 insertions, 158 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 3340bfb..8c85048 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2005-06-30  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/arm/arm.exp: Don't special case ldconst, arm7t, or copro
+	for *-wince-*.
+	* gas/arm/wince_arm7t.d, gas/arm/wince_copro.d
+	* gas/arm/wince_ldconst.d: Delete.
+
 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR 1013
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index 5fb82ad..123b813 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -18,16 +18,13 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
 
     if {[istarget *-wince-*]} then {
 	run_dump_test "wince_inst"
-	run_dump_test "wince_ldconst"
-	run_dump_test "wince_arm7t"
-	run_dump_test "wince_copro"
     } else {
 	run_dump_test "inst"
-	run_dump_test "ldconst"
-	run_dump_test "arm7t"
-	run_dump_test "copro"
     }
 
+    run_dump_test "ldconst"
+    run_dump_test "arm7t"
+    run_dump_test "copro"
     run_dump_test "arm3"
     run_dump_test "arm6"
     run_dump_test "arm7dm"
diff --git a/gas/testsuite/gas/arm/pic.d b/gas/testsuite/gas/arm/pic.d
index 5a87262..e50a716 100644
--- a/gas/testsuite/gas/arm/pic.d
+++ b/gas/testsuite/gas/arm/pic.d
@@ -8,7 +8,7 @@
 Disassembly of section .text:
 00+0 <[^>]*> eb...... 	bl	00+. <[^>]*>
 			0: R_ARM_PC24	foo.*
-00+4 <[^>]*> ebfffffe 	bl	0[0123456789abcdef]+ <[^>]*>
+00+4 <[^>]*> eb...... 	bl	0[0123456789abcdef]+ <[^>]*>
 			4: R_ARM_PLT32	foo
 	\.\.\.
 			8: R_ARM_ABS32	sym
diff --git a/gas/testsuite/gas/arm/wince_arm7t.d b/gas/testsuite/gas/arm/wince_arm7t.d
deleted file mode 100644
index 9d9b87f..0000000
--- a/gas/testsuite/gas/arm/wince_arm7t.d
+++ /dev/null
@@ -1,75 +0,0 @@
-#objdump: -Dr --prefix-addresses --show-raw-insn
-#name: ARM arm7t (WinCE version)
-#as: -mcpu=arm7t -EL
-#source: arm7t.s
-
-# This file is the same as arm7t.d except that the PC-relative
-# LDR[S]H instructions have not had a -8 bias inserted.
-
-
-# Test the halfword and signextend memory transfers:
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+00 <[^>]*> e1d100b0 ?	ldrh	r0, \[r1\]
-0+04 <[^>]*> e1f100b0 ?	ldrh	r0, \[r1\]!
-0+08 <[^>]*> e19100b2 ?	ldrh	r0, \[r1, r2\]
-0+0c <[^>]*> e1b100b2 ?	ldrh	r0, \[r1, r2\]!
-0+10 <[^>]*> e1d100bc ?	ldrh	r0, \[r1, #12\]
-0+14 <[^>]*> e1f100bc ?	ldrh	r0, \[r1, #12\]!
-0+18 <[^>]*> e15100bc ?	ldrh	r0, \[r1, #-12\]
-0+1c <[^>]*> e09100b2 ?	ldrh	r0, \[r1\], r2
-0+20 <[^>]*> e3a00cff ?	mov	r0, #65280	; 0xff00
-0+24 <[^>]*> e1df0abc ?	ldrh	r0, \[pc, #172\]	; 0+d8 <[^>]*>
-0+28 <[^>]*> e1df0abc ?	ldrh	r0, \[pc, #172\]	; 0+dc <[^>]*>
-0+2c <[^>]*> e1c100b0 ?	strh	r0, \[r1\]
-0+30 <[^>]*> e1e100b0 ?	strh	r0, \[r1\]!
-0+34 <[^>]*> e18100b2 ?	strh	r0, \[r1, r2\]
-0+38 <[^>]*> e1a100b2 ?	strh	r0, \[r1, r2\]!
-0+3c <[^>]*> e1c100bc ?	strh	r0, \[r1, #12\]
-0+40 <[^>]*> e1e100bc ?	strh	r0, \[r1, #12\]!
-0+44 <[^>]*> e14100bc ?	strh	r0, \[r1, #-12\]
-0+48 <[^>]*> e08100b2 ?	strh	r0, \[r1\], r2
-0+4c <[^>]*> e1cf08b8 ?	strh	r0, \[pc, #136\]	; 0+dc <[^>]*>
-0+50 <[^>]*> e1d100d0 ?	ldrsb	r0, \[r1\]
-0+54 <[^>]*> e1f100d0 ?	ldrsb	r0, \[r1\]!
-0+58 <[^>]*> e19100d2 ?	ldrsb	r0, \[r1, r2\]
-0+5c <[^>]*> e1b100d2 ?	ldrsb	r0, \[r1, r2\]!
-0+60 <[^>]*> e1d100dc ?	ldrsb	r0, \[r1, #12\]
-0+64 <[^>]*> e1f100dc ?	ldrsb	r0, \[r1, #12\]!
-0+68 <[^>]*> e15100dc ?	ldrsb	r0, \[r1, #-12\]
-0+6c <[^>]*> e09100d2 ?	ldrsb	r0, \[r1\], r2
-0+70 <[^>]*> e3a000de ?	mov	r0, #222	; 0xde
-0+74 <[^>]*> e1df06d0 ?	ldrsb	r0, \[pc, #96\]	; 0+dc <[^>]*>
-0+78 <[^>]*> e1d100f0 ?	ldrsh	r0, \[r1\]
-0+7c <[^>]*> e1f100f0 ?	ldrsh	r0, \[r1\]!
-0+80 <[^>]*> e19100f2 ?	ldrsh	r0, \[r1, r2\]
-0+84 <[^>]*> e1b100f2 ?	ldrsh	r0, \[r1, r2\]!
-0+88 <[^>]*> e1d100fc ?	ldrsh	r0, \[r1, #12\]
-0+8c <[^>]*> e1f100fc ?	ldrsh	r0, \[r1, #12\]!
-0+90 <[^>]*> e15100fc ?	ldrsh	r0, \[r1, #-12\]
-0+94 <[^>]*> e09100f2 ?	ldrsh	r0, \[r1\], r2
-0+98 <[^>]*> e3a00cff ?	mov	r0, #65280	; 0xff00
-0+9c <[^>]*> e1df03f4 ?	ldrsh	r0, \[pc, #52\]	; 0+d8 <[^>]*>
-0+a0 <[^>]*> e1df03f4 ?	ldrsh	r0, \[pc, #52\]	; 0+dc <[^>]*>
-0+a4 <[^>]*> e19100b2 ?	ldrh	r0, \[r1, r2\]
-0+a8 <[^>]*> 119100b2 ?	ldrneh	r0, \[r1, r2\]
-0+ac <[^>]*> 819100b2 ?	ldrhih	r0, \[r1, r2\]
-0+b0 <[^>]*> b19100b2 ?	ldrlth	r0, \[r1, r2\]
-0+b4 <[^>]*> e19100f2 ?	ldrsh	r0, \[r1, r2\]
-0+b8 <[^>]*> 119100f2 ?	ldrnesh	r0, \[r1, r2\]
-0+bc <[^>]*> 819100f2 ?	ldrhish	r0, \[r1, r2\]
-0+c0 <[^>]*> b19100f2 ?	ldrltsh	r0, \[r1, r2\]
-0+c4 <[^>]*> e19100d2 ?	ldrsb	r0, \[r1, r2\]
-0+c8 <[^>]*> 119100d2 ?	ldrnesb	r0, \[r1, r2\]
-0+cc <[^>]*> 819100d2 ?	ldrhisb	r0, \[r1, r2\]
-0+d0 <[^>]*> b19100d2 ?	ldrltsb	r0, \[r1, r2\]
-0+d4 <[^>]*> e15f00f4 ?	ldrsh	r0, \[pc, #-4\]	; 0+d8 <[^>]*>
-0+d8 <[^>]*> e15f00f4 ?	ldrsh	r0, \[pc, #-4\]	; 0+dc <[^>]*>
-0+dc <[^>]*> 00000000 ?	andeq	r0, r0, r0
-[		]*dc:.*fred
-0+e0 <[^>]*> 0000c0de ?	.*
-0+e4 <[^>]*> 0000dead ?	.*
-0+e8 <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
-0+ec <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/wince_copro.d b/gas/testsuite/gas/arm/wince_copro.d
deleted file mode 100644
index 91097dd..0000000
--- a/gas/testsuite/gas/arm/wince_copro.d
+++ /dev/null
@@ -1,45 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn --architecture=armv5te
-#name: ARM CoProcessor Instructions (WinCE version)
-#as: -march=armv5te -EL
-#source: copro.s
-
-# This file is the same as copro.d except that the PC-relative
-# LDC and STFS instructions have not had a -8 bias inserted.
-
-# Test the standard ARM co-processor instructions:
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+000 <[^>]*> ee421103 	dvfs	f1, f2, f3
-0+004 <[^>]*> 0e3414a5 	cfadddeq	mvd1, mvd4, mvd5
-0+008 <[^>]*> ed939500 	cfldr32	mvfx9, \[r3\]
-0+00c <[^>]*> edd1e108 	ldfp	f6, \[r1, #32\]
-0+010 <[^>]*> 4db200ff 	ldcmi	0, cr0, \[r2, #1020\]!
-0+014 <[^>]*> 5cf31710 	ldcpll	7, cr1, \[r3\], #64
-0+018 <[^>]*> ed1f8003 	ldc	0, cr8, \[pc, #-12\]
-0+01c <[^>]*> ed830500 	cfstr32	mvfx0, \[r3\]
-0+020 <[^>]*> edc0f302 	stcl	3, cr15, \[r0, #8\]
-0+024 <[^>]*> 0da2c419 	cfstrseq	mvf12, \[r2, #100\]!
-0+028 <[^>]*> 3ca4860c 	stccc	6, cr8, \[r4\], #48
-0+02c <[^>]*> ed0f7103 	stfs	f7, \[pc, #-12\]
-0+030 <[^>]*> ee715212 	mrc	2, 3, r5, cr1, cr2, \{0\}
-0+034 <[^>]*> aeb1f4f2 	mrcge	4, 5, pc, cr1, cr2, \{7\}
-0+038 <[^>]*> ee21f711 	mcr	7, 1, pc, cr1, cr1, \{0\}
-0+03c <[^>]*> be228519 	cfsh64lt	mvdx8, mvdx2, #9
-0+040 <[^>]*> ec907300 	ldc	3, cr7, \[r0\], \{0\}
-0+044 <[^>]*> ec816e01 	stc	14, cr6, \[r1\], \{1\}
-0+048 <[^>]*> fc925502 	ldc2	5, cr5, \[r2\], \{2\}
-0+04c <[^>]*> fc834603 	stc2	6, cr4, \[r3\], \{3\}
-0+050 <[^>]*> ecd43704 	ldcl	7, cr3, \[r4\], \{4\}
-0+054 <[^>]*> ecc52805 	stcl	8, cr2, \[r5\], \{5\}
-0+058 <[^>]*> fcd61906 	ldc2l	9, cr1, \[r6\], \{6\}
-0+05c <[^>]*> fcc70a07 	stc2l	10, cr0, \[r7\], \{7\}
-0+060 <[^>]*> ecd88bff 	ldcl	11, cr8, \[r8\], \{255\}
-0+064 <[^>]*> ecc99cfe 	stcl	12, cr9, \[r9\], \{254\}
-0+068 <[^>]*> ec507d04 	mrrc	13, 0, r7, r0, cr4
-0+06c <[^>]*> ec407e05 	mcrr	14, 0, r7, r0, cr5
-0+070 <[^>]*> ec507fff 	mrrc	15, 15, r7, r0, cr15
-0+074 <[^>]*> ec407efe 	mcrr	14, 15, r7, r0, cr14
-0+078 <[^>]*> e1a00000 	nop			\(mov r0,r0\)
-0+07c <[^>]*> e1a00000 	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/wince_ldconst.d b/gas/testsuite/gas/arm/wince_ldconst.d
deleted file mode 100644
index 131b4b5..0000000
--- a/gas/testsuite/gas/arm/wince_ldconst.d
+++ /dev/null
@@ -1,31 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: ARM ldr with immediate constant (WinCE version)
-#as: -mcpu=arm7m -EL
-#source: ldconst.s
-
-# This file is the same as ldconst.d except that the PC-
-# relative LDR instructions have not had a -8 bias inserted.
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+00 <[^>]*> e3a00000 ?	mov	r0, #0	; 0x0
-0+04 <[^>]*> e3a004ff ?	mov	r0, #-16777216	; 0xff000000
-0+08 <[^>]*> e3e00000 ?	mvn	r0, #0	; 0x0
-0+0c <[^>]*> e51f000c ?	ldr	r0, \[pc, #-12\]	; 0+08 <[^>]*>
-0+10 <[^>]*> 0fff0000 ?	.*
-0+14 <[^>]*> e3a0e000 ?	mov	lr, #0	; 0x0
-0+18 <[^>]*> e3a0e8ff ?	mov	lr, #16711680	; 0xff0000
-0+1c <[^>]*> e3e0e8ff ?	mvn	lr, #16711680	; 0xff0000
-0+20 <[^>]*> e51fe00c ?	ldr	lr, \[pc, #-12\]	; 0+1c <[^>]*>
-0+24 <[^>]*> 00fff000 ?	.*
-0+28 <[^>]*> 03a00000 ?	moveq	r0, #0	; 0x0
-0+2c <[^>]*> 03a00cff ?	moveq	r0, #65280	; 0xff00
-0+30 <[^>]*> 03e00cff ?	mvneq	r0, #65280	; 0xff00
-0+34 <[^>]*> 051f000c ?	ldreq	r0, \[pc, #-12\]	; 0+30 <[^>]*>
-0+38 <[^>]*> 000fff00 ?	.*
-0+3c <[^>]*> 43a0b000 ?	movmi	fp, #0	; 0x0
-0+40 <[^>]*> 43a0b0ff ?	movmi	fp, #255	; 0xff
-0+44 <[^>]*> 43e0b0ff ?	mvnmi	fp, #255	; 0xff
-0+48 <[^>]*> 451fb00c ?	ldrmi	fp, \[pc, #-12\]	; 0+44 <[^>]*>
-0+4c <[^>]*> 0000fff0 ?	.*