RISC-V: Support to add implicit extensions for G.

G is a special case, consider the ISA spec github issue as follows,
https://github.com/riscv/riscv-isa-manual/issues/575

My understand is that - i, m, a, f and d extensions are not g's implicit
extensions, they are g's expansions.  The zifencei is the implicit extension
of g, and so is zicsr, since it is implicited by f (or i2p1).  However,
we add the g with the RISCV_UNKNOWN_VERSION to the subset list, and it
will not output to the arch string, it is only used to check what implicit
extensions are need to be added.

	bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow to add g with
	RISCV_UNKNOWN_VERSION versions.
	(riscv_parse_std_ext): Add g to the subset list, we only use it
	to add the implicit extensions, but won't output it to arch string.
	(riscv_parse_add_implicit_subsets): Add implicit zicsr and zifencei
	for g extension.
	(riscv_arch_str1): Do not output g to the arch string.
	* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Moved to include/opcode/riscv.h.

	gas/
	* testsuite/gas/riscv/attribute-10.d: Updated.
	* testsuite/gas/riscv/march-imply-g.d: New testcase for g.
	* testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei
	are not supported in the ISA spec v2.2, so don't add and output them.

	include/
	* opcode/riscv.h (RISCV_UNKNOWN_VERSION): added.

3 files changed, 13 insertions, 1 deletions

diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
index ba903d1..30b82d7 100644
--- a/gas/testsuite/gas/riscv/attribute-10.d
+++ b/gas/testsuite/gas/riscv/attribute-10.d
@@ -3,4 +3,4 @@
 #source: empty.s
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-g.d b/gas/testsuite/gas/riscv/march-imply-g.d
new file mode 100644
index 0000000..33a243d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-g.d
@@ -0,0 +1,6 @@
+#as: -march=rv32g -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d b/gas/testsuite/gas/riscv/march-imply-unsupported.d
new file mode 100644
index 0000000..2e19e09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-unsupported.d
@@ -0,0 +1,6 @@
+#as: -march=rv32g -march-attr -misa-spec=2.2
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"