Add MIPS32 as a seperate MIPS architecture

2 files changed, 15 insertions, 18 deletions

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index a45a561..a59ae1d 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -276,7 +276,8 @@ Here is a brief summary of how to invoke @code{@value{AS}}.  For details,
 @end ifset
 @ifset MIPS
  [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
- [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ] [ -mips32 ] [ -no-mips32 ]
+ [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips32 ]
+ [ -m4650 ] [ -no-m4650 ]
  [ --trap ] [ --break ]
  [ --emulation=@var{name} ]
 @end ifset
@@ -669,10 +670,12 @@ Generate ``little endian'' format output.
 @item -mips1
 @itemx -mips2
 @itemx -mips3
+@itemx -mips4
+@itemx -mips32
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
-@samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000}
-processor.
+@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000}
+processor, @samp{-mips32} to a generic @sc{MIPS32} processor.
 
 @item -m4650
 @itemx -no-m4650
@@ -681,12 +684,6 @@ the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
 instructions around accesses to the @samp{HI} and @samp{LO} registers.
 @samp{-no-m4650} turns off this option.
 
-@item -mips32
-@itemx -no-mips32
-Generate code for the @sc{MIPS32} architecture. This tells the assembler to
-accept ISA level 2 instructions and MIPS32 extensions including some @sc{r4000}
-instructions.
-
 @item -mcpu=@var{CPU}
 Generate code for a particular MIPS cpu.  This has little effect on the
 assembler, but it is passed by @code{@value{GCC}}.
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 137dfe9..e56156e 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -60,12 +60,14 @@ to select big-endian output, and @samp{-EL} for little-endian.
 @itemx -mips2
 @itemx -mips3
 @itemx -mips4
+@itemx -mips32
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
-@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
-@sc{r10000} processors.  You can also switch instruction sets during the
-assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
+@sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and
+@sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32)
+processor.  You can also switch instruction sets during the
+assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
 
 @item -mgp32
 Assume that 32-bit general purpose registers are available.  This
@@ -140,10 +142,8 @@ rm5721,
 6000,
 rm7000,
 8000,
-10000
-4Kc
-4Km
-4Kp
+10000,
+mips32-4k
 @end quotation
 
 
@@ -239,8 +239,8 @@ assembly language programmers!
 @kindex @code{.set mips@var{n}}
 @sc{gnu} @code{@value{AS}} supports an additional directive to change
 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
-mips@var{n}}.  @var{n} should be a number from 0 to 4.  A value from 1
-to 4 makes the assembler accept instructions for the corresponding
+mips@var{n}}.  @var{n} should be a number from 0 to 4, or 32.  The values 1
+to 4 and 32 make the assembler accept instructions for the corresponding
 @sc{isa} level, from that point on in the assembly.  @code{.set
 mips@var{n}} affects not only which instructions are permitted, but also
 how certain macros are expanded.  @code{.set mips0} restores the