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| author | Jose E. Marchesi <jose.marchesi@oracle.com> | 2023-07-21 19:47:49 +0200 |
|---|---|---|
| committer | Jose E. Marchesi <jose.marchesi@oracle.com> | 2023-07-21 20:00:30 +0200 |
| commit | c24fd9547fb6836af022c99470dfdb13fa9f90fe (patch) | |
| tree | 7267743504eb02a63dc11928aa08d80936a203c4 /gas/doc | |
| parent | 2f3dbc5fb5e781fc17d8f68f9c960a993f06d801 (diff) | |
| download | gdb-c24fd9547fb6836af022c99470dfdb13fa9f90fe.zip gdb-c24fd9547fb6836af022c99470dfdb13fa9f90fe.tar.gz gdb-c24fd9547fb6836af022c99470dfdb13fa9f90fe.tar.bz2 | |
bpf: opcodes, gas: support for signed load V4 instructions
This commit adds the signed load to register (ldxs*) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
instructions.
(BPF_MODE_SMEM): Define.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Add signed load instructions.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document the signed load
instructions.
Diffstat (limited to 'gas/doc')
| -rw-r--r-- | gas/doc/c-bpf.texi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index a3814e9..bebf760 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -483,6 +483,26 @@ Generic 16-bit load. Generic 8-bit load. @end table +Signed load to register instructions: + +@table @code +@item ldxsdw rd, [rs + offset16] +@itemx rd = *(i64 *) (rs + offset16) +Generic 64-bit signed load. + +@item ldxsw rd, [rs + offset16] +@itemx rd = *(i32 *) (rs + offset16) +Generic 32-bit signed load. + +@item ldxsh rd, [rs + offset16] +@itemx rd = *(i16 *) (rs + offset16) +Generic 16-bit signed load. + +@item ldxsb rd, [rs + offset16] +@itemx rd = *(i8 *) (rs + offset16) +Generic 8-bit signed load. +@end table + Store from register instructions: @table @code |