[ gas/ChangeLog ]

	* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
	(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
	ISA_HAS_MXHC1): New macros.
	(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
	ISA_HAS_64BIT_REGS.  Formatting fixes.  Improved comments.
	(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
	(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
	MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
	(mips_after_parse_args): Change default handling of float register
	size to account for 32bit code with 64bit FP. Better sanity checking
	of ISA/ASE/ABI option combinations.
	(s_mipsset): Support switching of GPR and FPR sizes via
	.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
	options.
	(mips_elf_final_processing): We should record the use of 64bit FP
	registers in 32bit code but we don't, because ELF header flags are
	a scarce ressource.
	(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
	extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
	24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
	(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
	* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
	missing -march options. Document .set arch=CPU. Move .set smartmips
	to ASE page. Use @code for .set FOO examples.

	[ gas/testsuite/Changelog ]
	* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
	gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
	gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
	output.
	* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
	catch assembler warnings.

1 files changed, 60 insertions, 16 deletions

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 7ba7496..383bba4 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -91,19 +91,28 @@ flags force a certain group of registers to be treated as 32 bits wide at
 all times.  @samp{-mgp32} controls the size of general-purpose registers
 and @samp{-mfp32} controls the size of floating-point registers.
 
+The @code{.set gp=32} and @code{.set fp=32} directives allow the size
+of registers to be changed for parts of an object. The default value is
+restored by @code{.set gp=default} and @code{.set fp=default}.
+
 On some MIPS variants there is a 32-bit mode flag; when this flag is
 set, 64-bit instructions generate a trap.  Also, some 32-bit OSes only
 save the 32-bit registers on a context switch, so it is essential never
 to use the 64-bit registers.
 
 @item -mgp64
-Assume that 64-bit general purpose registers are available.  This is
-provided in the interests of symmetry with -gp32.
+@itemx -mfp64
+Assume that 64-bit registers are available.  This is provided in the
+interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
+
+The @code{.set gp=64} and @code{.set fp=64} directives allow the size
+of registers to be changed for parts of an object. The default value is
+restored by @code{.set gp=default} and @code{.set fp=default}.
 
 @item -mips16
 @itemx -no-mips16
 Generate code for the MIPS 16 processor.  This is equivalent to putting
-@samp{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
+@code{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
 turns off this option.
 
 @item -msmartmips
@@ -111,7 +120,7 @@ turns off this option.
 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
 provides a number of new instructions which target smartcard and
 cryptographic applications.  This is equivalent to putting
-@samp{.set smartmips} at the start of the assembly file.
+@code{.set smartmips} at the start of the assembly file.
 @samp{-mno-smartmips} turns off this option.
 
 @item -mips3d
@@ -210,7 +219,29 @@ rm7000,
 rm9000,
 10000,
 12000,
-mips32-4k,
+4kc,
+4km,
+4kp,
+4ksc,
+4kec,
+4kem,
+4kep,
+4ksd,
+m4k,
+m4kp,
+24kc,
+24kf,
+24kx,
+24kec,
+24kef,
+24kex,
+34kc,
+34kf,
+34kx,
+5kc,
+5kf,
+20kc,
+25kf,
 sb1
 @end quotation
 
@@ -399,17 +430,21 @@ assembly.  @code{.set mips@var{n}} affects not only which instructions
 are permitted, but also how certain macros are expanded.  @code{.set
 mips0} restores the @sc{isa} level to its original level: either the
 level you selected with command line options, or the default for your
-configuration.  You can use this feature to permit specific @sc{r4000}
+configuration.  You can use this feature to permit specific @sc{mips3}
 instructions while assembling in 32 bit mode.  Use this directive with
 care!
 
-The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
-in which it will assemble instructions for the MIPS 16 processor.  Use
-@samp{.set nomips16} to return to normal 32 bit mode.
+@cindex MIPS CPU override
+@kindex @code{.set arch=@var{cpu}}
+The @code{.set arch=@var{cpu}} directive provides even finer control.
+It changes the effective CPU target and allows the assembler to use
+instructions specific to a particular CPU.  All CPUs supported by the
+@samp{-march} command line option are also selectable by this directive.
+The original value is restored by @code{.set arch=default}.
 
-The @samp{.set smartmips} directive enables use of the SmartMIPS
-extensions to the MIPS32 @sc{isa}; the @samp{.set nosmartmips} directive
-reverses that.
+The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
+in which it will assemble instructions for the MIPS 16 processor.  Use
+@code{.set nomips16} to return to normal 32 bit mode.
 
 Traditional @sc{mips} assemblers do not support this directive.
 
@@ -419,10 +454,10 @@ Traditional @sc{mips} assemblers do not support this directive.
 @kindex @code{.set autoextend}
 @kindex @code{.set noautoextend}
 By default, MIPS 16 instructions are automatically extended to 32 bits
-when necessary.  The directive @samp{.set noautoextend} will turn this
-off.  When @samp{.set noautoextend} is in effect, any 32 bit instruction
-must be explicitly extended with the @samp{.e} modifier (e.g.,
-@samp{li.e $4,1000}).  The directive @samp{.set autoextend} may be used
+when necessary.  The directive @code{.set noautoextend} will turn this
+off.  When @code{.set noautoextend} is in effect, any 32 bit instruction
+must be explicitly extended with the @code{.e} modifier (e.g.,
+@code{li.e $4,1000}).  The directive @code{.set autoextend} may be used
 to once again automatically extend instructions when necessary.
 
 This directive is only meaningful when in MIPS 16 mode.  Traditional
@@ -467,6 +502,15 @@ from the MIPS-3D Application Specific Extension from that point on
 in the assembly.  The @code{.set nomips3d} directive prevents MIPS-3D
 instructions from being accepted.
 
+@cindex SmartMIPS instruction generation override
+@kindex @code{.set smartmips}
+@kindex @code{.set nosmartmips}
+The directive @code{.set smartmips} makes the assembler accept
+instructions from the SmartMIPS Application Specific Extension to the
+MIPS32 @sc{isa} from that point on in the assembly.  The
+@code{.set nosmartmips} directive prevents SmartMIPS instructions from
+being accepted.
+
 @cindex MIPS MDMX instruction generation override
 @kindex @code{.set mdmx}
 @kindex @code{.set nomdmx}