RISC-V: Extend .insn directive to support hardcode encoding.

The .insn directive can let users use their own instructions, or
some new instruction, which haven't supported in the old binutils.
For example, if users want to use sifive cache instruction, they
cannot just write "cflush.d1.l1" in the assembly code, they should
use ".insn i SYSTEM, 0, x0, x10, -0x40".  But the .insn directive
may not easy to use for some cases, and not so friendly to users.
Therefore, I believe most of the users will use ".word 0xfc050073",
to encode the instructions directly, rather than use .insn.  But
once we have supported the mapping symbols, the .word directives
are marked as data, so disassembler won't dump them as instructions
as usual.  I have discussed this with Kito many times, we all think
extend the .insn direcitve to support the hardcode encoding, is the
easiest way to resolve the problem.  Therefore, there are two more
.insn formats are proposed as follows,

(original) .insn <type>, <operand1>, <operand2>, ...
           .insn <insn-length>, <value>
           .insn <value>

The <type> is string, and the <insn-length> and <value> are constants.

gas/
	* config/tc-riscv.c (riscv_ip_hardcode): Similar to riscv_ip,
	but assembles an instruction according to the hardcode values
	of .insn directive.
	* doc/c-riscv.texi: Document two new .insn formats.
	* testsuite/gas/riscv/insn-fail.d: New testcases.
	* testsuite/gas/riscv/insn-fail.l: Likewise.
	* testsuite/gas/riscv/insn-fail.s: Likewise.
	* testsuite/gas/riscv/insn.d: Updated.
	* testsuite/gas/riscv/insn.s: Likewise.

1 files changed, 12 insertions, 2 deletions

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index c15297e..bfbf61d 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -213,13 +213,23 @@ desirable.
 Enables or disables the CSR checking.
 
 @cindex INSN directives
-@item .insn @var{value}
+@item .insn @var{type}, @var{operand} [,...,@var{operand_n}]
+@itemx .insn @var{insn_length}, @var{value}
 @itemx .insn @var{value}
 This directive permits the numeric representation of an instructions
 and makes the assembler insert the operands according to one of the
 instruction formats for @samp{.insn} (@ref{RISC-V-Formats}).
 For example, the instruction @samp{add a0, a1, a2} could be written as
-@samp{.insn r 0x33, 0, 0, a0, a1, a2}.
+@samp{.insn r 0x33, 0, 0, a0, a1, a2}.  But in fact, the instruction
+formats are difficult to use for some users, so most of them are using
+@samp{.word} to encode the instruction directly, rather than using
+@samp{.insn}.  It is fine for now, but will be wrong when the mapping
+symbols are supported, since @samp{.word} will not be shown as an
+instruction, it should be shown as data.  Therefore, we also support
+two more formats of the @samp{.insn}, the instruction @samp{add a0, a1, a2}
+could also be written as @samp{.insn 0x4, 0xc58533} or @samp{.insn 0xc58533}.
+When the @var{insn_length} is set, then assembler will check if the
+@var{value} is a valid @var{insn_length} bytes instruction.
 
 @cindex @code{.attribute} directive, RISC-V
 @item .attribute @var{tag}, @var{value}