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author | Nelson Chu <nelson.chu@sifive.com> | 2021-01-26 18:02:38 +0800 |
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committer | Nelson Chu <nelson.chu@sifive.com> | 2021-02-19 11:44:49 +0800 |
commit | 5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa (patch) | |
tree | 7fd17df7fe3b4eb80cb7dc6d03087b7a5c04857a /gas/doc | |
parent | 2f973f134d7752cbc662ec65da8ad8bbe4c6fb8f (diff) | |
download | gdb-5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa.zip gdb-5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa.tar.gz gdb-5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa.tar.bz2 |
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,
[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM: Renamed from SBTYPE_IMM.
JTYPE_IMM: Renamed from UJTYPE_IMM.
CITYPE_IMM: Renamed from RVC_IMM.
CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM: Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM: Added for .insn without special encoding.
CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM.
CLTYPE_IMM: Added for .insn without special encoding.
CLTYPE_LW_IMM: Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM: Renamed from RVC_LD_IMM.
RVC_SIMM3: Unused and removed.
CBTYPE_IMM: Renamed from RVC_B_IMM.
CJTYPE_IMM: Renamed from RVC_J_IMM.
* Added new operands and removed the unused ones,
C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.
bfd/
PR 27158
* elfnn-riscv.c (perform_relocation): Updated encoding macros.
(_bfd_riscv_relax_call): Likewise.
(_bfd_riscv_relax_lui): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
gas/
PR 27158
* config/tc-riscv.c (riscv_ip): Updated encoding macros.
(md_apply_fix): Likewise.
(md_convert_frag_branch): Likewise.
(validate_riscv_insn): Likewise. Also arranged operands, including
added C5 and C6 operands, and removed unused Ci and C< operands.
* doc/c-riscv.texi: Updated and added CSS/CL/CS types.
* testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
* testsuite/gas/riscv/insn.s: Likewise.
gdb/
PR 27158
* riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
(decode_j_type_insn): Likewise.
(decode_cj_type_insn): Likewise.
(decode_b_type_insn): Likewise.
(decode): Likewise.
include/
PR 27158
* opcode/riscv.h: Updated encoding macros.
opcodes/
PR 27158
* riscv-dis.c (print_insn_args): Updated encoding macros.
* riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
(match_c_addi16sp): Updated encoding macros.
(match_c_lui): Likewise.
(match_c_lui_with_hint): Likewise.
(match_c_addi4spn): Likewise.
(match_c_slli): Likewise.
(match_slli_as_c_slli): Likewise.
(match_c_slli64): Likewise.
(match_srxi_as_c_srxi): Likewise.
(riscv_insn_types): Added .insn css/cl/cs.
sim/
PR 27158
* riscv/sim-main.c (execute_i): Updated encoding macros.
Diffstat (limited to 'gas/doc')
-rw-r--r-- | gas/doc/c-riscv.texi | 160 |
1 files changed, 93 insertions, 67 deletions
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index e945482..c15297e 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -363,7 +363,7 @@ The pseudo la.tls.gd instruction can be expended to @cindex instruction formats, risc-v @cindex RISC-V instruction formats -The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12 +The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15 instruction formats where some of the formats have multiple variants. For the @samp{.insn} pseudo directive the assembler recognizes some of the formats. @@ -394,6 +394,8 @@ only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. @item simm12 @tab Sign-extended 12-bit immediate for operand x. @item simm20 @tab Sign-extended 20-bit immediate for operand x. @item simm6 @tab Sign-extended 6-bit immediate for operand x. +@item uimm5 @tab Unsigned 5-bit immediate for operand x. +@item uimm6 @tab Unsigned 6-bit immediate for operand x. @item uimm8 @tab Unsigned 8-bit immediate for operand x. @item symbol @tab Symbol or lable reference for operand x. @end multitable @@ -487,112 +489,136 @@ The following table lists the RISC-V instruction formats that are available with the @samp{.insn} pseudo directive: @table @code -@item R type: .insn r opcode, func3, func7, rd, rs1, rs2 +@item R type: .insn r opcode6, func3, func7, rd, rs1, rs2 @verbatim -+-------+-----+-----+-------+----+-------------+ -| func7 | rs2 | rs1 | func3 | rd | opcode | -+-------+-----+-----+-------+----+-------------+ -31 25 20 15 12 7 0 ++-------+-----+-----+-------+----+---------+ +| func7 | rs2 | rs1 | func3 | rd | opcode6 | ++-------+-----+-----+-------+----+---------+ +31 25 20 15 12 7 0 @end verbatim -@item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3 -@itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3 +@item R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3 +@itemx R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3 @verbatim -+-----+-------+-----+-----+-------+----+-------------+ -| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode | -+-----+-------+-----+-----+-------+----+-------------+ -31 27 25 20 15 12 7 0 ++-----+-------+-----+-----+-------+----+---------+ +| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 | ++-----+-------+-----+-----+-------+----+---------+ +31 27 25 20 15 12 7 0 @end verbatim -@item I type: .insn i opcode, func3, rd, rs1, simm12 -@itemx I type: .insn i opcode, func3, rd, simm12(rs1) +@item I type: .insn i opcode6, func3, rd, rs1, simm12 +@itemx I type: .insn i opcode6, func3, rd, simm12(rs1) @verbatim -+-------------+-----+-------+----+-------------+ -| simm12 | rs1 | func3 | rd | opcode | -+-------------+-----+-------+----+-------------+ -31 20 15 12 7 0 ++--------------+-----+-------+----+---------+ +| simm12[11:0] | rs1 | func3 | rd | opcode6 | ++--------------+-----+-------+----+---------+ +31 20 15 12 7 0 @end verbatim -@item S type: .insn s opcode, func3, rs2, simm12(rs1) +@item S type: .insn s opcode6, func3, rs2, simm12(rs1) @verbatim -+--------------+-----+-----+-------+-------------+-------------+ -| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode | -+--------------+-----+-----+-------+-------------+-------------+ -31 25 20 15 12 7 0 ++--------------+-----+-----+-------+-------------+---------+ +| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 | ++--------------+-----+-----+-------+-------------+---------+ +31 25 20 15 12 7 0 @end verbatim -@item B type: .insn s opcode, func3, rs1, rs2, symbol -@itemx SB type: .insn sb opcode, func3, rs1, rs2, symbol +@item B type: .insn s opcode6, func3, rs1, rs2, symbol +@itemx SB type: .insn sb opcode6, func3, rs1, rs2, symbol @verbatim -+------------+--------------+-----+-----+-------+-------------+-------------+--------+ -| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode | -+------------+--------------+-----+-----+-------+-------------+-------------+--------+ -31 30 25 20 15 12 7 0 ++-----------------+-----+-----+-------+----------------+---------+ +| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 | ++-----------------+-----+-----+-------+----------------+---------+ +31 25 20 15 12 7 0 @end verbatim -@item U type: .insn u opcode, rd, simm20 +@item U type: .insn u opcode6, rd, simm20 @verbatim -+---------------------------+----+-------------+ -| simm20 | rd | opcode | -+---------------------------+----+-------------+ -31 12 7 0 ++--------------------------+----+---------+ +| simm20[20|10:1|11|19:12] | rd | opcode6 | ++--------------------------+----+---------+ +31 12 7 0 @end verbatim -@item J type: .insn j opcode, rd, symbol -@itemx UJ type: .insn uj opcode, rd, symbol +@item J type: .insn j opcode6, rd, symbol +@itemx UJ type: .insn uj opcode6, rd, symbol @verbatim -+------------+--------------+------------+---------------+----+-------------+ -| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode | -+------------+--------------+------------+---------------+----+-------------+ -31 30 21 20 12 7 0 ++------------+--------------+------------+---------------+----+---------+ +| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 | ++------------+--------------+------------+---------------+----+---------+ +31 30 21 20 12 7 0 @end verbatim @item CR type: .insn cr opcode2, func4, rd, rs2 @verbatim -+---------+--------+-----+---------+ -| func4 | rd/rs1 | rs2 | opcode2 | -+---------+--------+-----+---------+ -15 12 7 2 0 ++-------+--------+-----+---------+ +| func4 | rd/rs1 | rs2 | opcode2 | ++-------+--------+-----+---------+ +15 12 7 2 0 @end verbatim @item CI type: .insn ci opcode2, func3, rd, simm6 @verbatim -+---------+-----+--------+-----+---------+ -| func3 | imm | rd/rs1 | imm | opcode2 | -+---------+-----+--------+-----+---------+ -15 13 12 7 2 0 ++-------+----------+--------+------------+---------+ +| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 | ++-------+----------+--------+------------+---------+ +15 13 12 7 2 0 @end verbatim -@item CIW type: .insn ciw opcode2, func3, rd, uimm8 +@item CIW type: .insn ciw opcode2, func3, rd', uimm8 @verbatim -+---------+--------------+-----+---------+ -| func3 | imm | rd' | opcode2 | -+---------+--------------+-----+---------+ -15 13 7 2 0 ++-------+------------+-----+---------+ +| func3 | uimm8[7:0] | rd' | opcode2 | ++-------+-------- ---+-----+---------+ +15 13 5 2 0 @end verbatim -@item CA type: .insn ca opcode2, func6, func2, rd, rs2 +@item CSS type: .insn css opcode2, func3, rd, uimm6 @verbatim -+---------+----------+-------+------+--------+ -| func6 | rd'/rs1' | func2 | rs2' | opcode | -+---------+----------+-------+------+--------+ -15 10 7 5 2 0 ++-------+------------+----+---------+ +| func3 | uimm6[5:0] | rd | opcode2 | ++-------+------------+----+---------+ +15 13 7 2 0 @end verbatim -@item CB type: .insn cb opcode2, func3, rs1, symbol +@item CL type: .insn cl opcode2, func3, rd', uimm5(rs1') @verbatim -+---------+--------+------+--------+---------+ -| func3 | offset | rs1' | offset | opcode2 | -+---------+--------+------+--------+---------+ -15 13 10 7 2 0 ++-------+------------+------+------------+------+---------+ +| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 | ++-------+------------+------+------------+------+---------+ +15 13 10 7 5 2 0 +@end verbatim + +@item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1') +@verbatim ++-------+------------+------+------------+------+---------+ +| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 | ++-------+------------+------+------------+------+---------+ +15 13 10 7 5 2 0 +@end verbatim + +@item CA type: .insn ca opcode2, func6, func2, rd', rs2' +@verbatim ++-- ----+----------+-------+------+---------+ +| func6 | rd'/rs1' | func2 | rs2' | opcode2 | ++-------+----------+-------+------+---------+ +15 10 7 5 2 0 +@end verbatim + +@item CB type: .insn cb opcode2, func3, rs1', symbol +@verbatim ++-------+--------------+------+------------------+---------+ +| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 | ++-------+--------------+------+------------------+---------+ +15 13 10 7 2 0 @end verbatim @item CJ type: .insn cj opcode2, symbol @verbatim -+---------+--------------------+---------+ -| func3 | jump target | opcode2 | -+---------+--------------------+---------+ -15 13 7 2 0 ++-------+-------------------------------+---------+ +| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 | ++-------+-------------------------------+---------+ +15 13 2 0 @end verbatim |