Fix spelling mistakes and typos in the GAS sources.

	PR gas/21072
	* asintl.h: Fix spelling mistakes and typos.
	* atof-generic.c: Likewise.
	* bit_fix.h: Likewise.
	* config/atof-ieee.c: Likewise.
	* config/bfin-defs.h: Likewise.
	* config/bfin-parse.y: Likewise.
	* config/obj-coff-seh.h: Likewise.
	* config/obj-coff.c: Likewise.
	* config/obj-evax.c: Likewise.
	* config/obj-macho.c: Likewise.
	* config/rx-parse.y: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-avr.c: Likewise.
	* config/tc-bfin.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-cris.c: Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-d10v.c: Likewise.
	* config/tc-d30v.c: Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-epiphany.c: Likewise.
	* config/tc-frv.c: Likewise.
	* config/tc-hppa.c: Likewise.
	* config/tc-i370.c: Likewise.
	* config/tc-i386-intel.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m32r.c: Likewise.
	* config/tc-m68hc11.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mcore.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-mep.h: Likewise.
	* config/tc-metag.c: Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-mmix.c: Likewise.
	* config/tc-mn10200.c: Likewise.
	* config/tc-mn10300.c: Likewise.
	* config/tc-msp430.c: Likewise.
	* config/tc-msp430.h: Likewise.
	* config/tc-nds32.c: Likewise.
	* config/tc-nds32.h: Likewise.
	* config/tc-nios2.c: Likewise.
	* config/tc-nios2.h: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-pdp11.c: Likewise.
	* config/tc-ppc.c: Likewise.
	* config/tc-pru.c: Likewise.
	* config/tc-rx.c: Likewise.
	* config/tc-s390.c: Likewise.
	* config/tc-score.c: Likewise.
	* config/tc-score7.c: Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-sh64.c: Likewise.
	* config/tc-sparc.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-tic54x.c: Likewise.
	* config/tc-v850.c: Likewise.
	* config/tc-vax.c: Likewise.
	* config/tc-visium.c: Likewise.
	* config/tc-xgate.c: Likewise.
	* config/tc-xtensa.c: Likewise.
	* config/tc-z80.c: Likewise.
	* config/tc-z8k.c: Likewise.
	* config/te-vms.c: Likewise.
	* config/xtensa-relax.c: Likewise.
	* doc/as.texinfo: Likewise.
	* doc/c-arm.texi: Likewise.
	* doc/c-hppa.texi: Likewise.
	* doc/c-i370.texi: Likewise.
	* doc/c-i386.texi: Likewise.
	* doc/c-m32r.texi: Likewise.
	* doc/c-m68k.texi: Likewise.
	* doc/c-mmix.texi: Likewise.
	* doc/c-msp430.texi: Likewise.
	* doc/c-nds32.texi: Likewise.
	* doc/c-ns32k.texi: Likewise.
	* doc/c-riscv.texi: Likewise.
	* doc/c-rx.texi: Likewise.
	* doc/c-s390.texi: Likewise.
	* doc/c-tic6x.texi: Likewise.
	* doc/c-tilegx.texi: Likewise.
	* doc/c-tilepro.texi: Likewise.
	* doc/c-v850.texi: Likewise.
	* doc/c-xgate.texi: Likewise.
	* doc/c-xtensa.texi: Likewise.
	* dwarf2dbg.c: Likewise.
	* ecoff.c: Likewise.
	* itbl-ops.c: Likewise.
	* listing.c: Likewise.
	* macro.c: Likewise.
	* po/gas.pot: Likewise.
	* read.c: Likewise.
	* struc-symbol.h: Likewise.
	* symbols.h: Likewise.
	* testsuite/gas/arc/relocs-errors.err: Likewise.
	* write.c: Likewise.

20 files changed, 34 insertions, 34 deletions

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index eb43723..5e30fc4 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -4876,7 +4876,7 @@ CFA address.
 
 @subsection @code{.cfi_adjust_cfa_offset @var{offset}}
 Same as @code{.cfi_def_cfa_offset} but @var{offset} is a relative
-value that is added/substracted from the previous offset.
+value that is added/subtracted from the previous offset.
 
 @subsection @code{.cfi_offset @var{register}, @var{offset}}
 Previous value of @var{register} is saved at offset @var{offset} from
@@ -5178,7 +5178,7 @@ The syntax for @code{equ} on the HPPA is
 @ifset Z80
 The syntax for @code{equ} on the Z80 is
 @samp{@var{symbol} equ @var{expression}}.
-On the Z80 it is an eror if @var{symbol} is already defined,
+On the Z80 it is an error if @var{symbol} is already defined,
 but the symbol is not protected from later redefinition.
 Compare @ref{Equiv}.
 @end ifset
@@ -6495,8 +6495,8 @@ exception_code
 
 The two @code{exception_code} invocations above would create the
 @code{.text.exception} and @code{.init.exception} sections respectively.
-This is useful e.g. to discriminate between anciliary sections that are
-tied to setup code to be discarded after use from anciliary sections that
+This is useful e.g. to discriminate between ancillary sections that are
+tied to setup code to be discarded after use from ancillary sections that
 need to stay resident without having to define multiple @code{exception_code}
 macros just for that purpose.
 
@@ -7126,7 +7126,7 @@ Mark the symbol as being a data object.
 
 @item STT_TLS
 @itemx tls_object
-Mark the symbol as being a thead-local data object.
+Mark the symbol as being a thread-local data object.
 
 @item STT_COMMON
 @itemx common
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 5437a55..391c396 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -188,7 +188,7 @@ architectures),
 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
 @code{virt} (Virtualization Extensions for v7-A architecture, implies
 @code{idiv}),
-@code{pan} (Priviliged Access Never Extensions for v8-A architecture),
+@code{pan} (Privileged Access Never Extensions for v8-A architecture),
 @code{ras} (Reliability, Availability and Serviceability extensions
 for v8-A architecture),
 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
@@ -935,7 +935,7 @@ between Arm and Thumb instructions and should be used even if
 interworking is not going to be performed.  The presence of this
 directive also implies @code{.thumb}
 
-This directive is not neccessary when generating EABI objects.  On these
+This directive is not necessary when generating EABI objects.  On these
 targets the encoding is implicit when generating Thumb code.
 
 @cindex @code{.thumb_set} directive, ARM
@@ -970,7 +970,7 @@ should only be done if it is really necessary.
 
 @cindex @code{.unwind_raw} directive, ARM
 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
-Insert one of more arbitary unwind opcode bytes, which are known to adjust
+Insert one of more arbitrary unwind opcode bytes, which are known to adjust
 the stack pointer by @var{offset} bytes.
 
 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
diff --git a/gas/doc/c-hppa.texi b/gas/doc/c-hppa.texi
index 8331c3a..34a3d6a 100644
--- a/gas/doc/c-hppa.texi
+++ b/gas/doc/c-hppa.texi
@@ -17,7 +17,7 @@
 
 @node HPPA Notes
 @section Notes
-As a back end for @sc{gnu} @sc{cc} @code{@value{AS}} has been throughly tested and should
+As a back end for @sc{gnu} @sc{cc} @code{@value{AS}} has been thoroughly tested and should
 work extremely well.  We have tested it only minimally on hand written assembly
 code and no one has tested it much on the assembly output from the HP
 compilers.
diff --git a/gas/doc/c-i370.texi b/gas/doc/c-i370.texi
index 3d86c39..6b965d5 100644
--- a/gas/doc/c-i370.texi
+++ b/gas/doc/c-i370.texi
@@ -66,7 +66,7 @@ write code.
 Since @samp{$} has no special meaning, you may use it in symbol names.
 
 Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6.
-By using thesse symbolic names, @code{@value{AS}} can detect simple
+By using these symbolic names, @code{@value{AS}} can detect simple
 syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca
 for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
 for r3 and rpgt or r.pgt for r4.
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index d4e0294..2cbffb9 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -317,7 +317,7 @@ take precedent.
 @cindex @samp{-mnaked-reg} option, i386
 @cindex @samp{-mnaked-reg} option, x86-64
 @item -mnaked-reg
-This opetion specifies that registers don't require a @samp{%} prefix.
+This option specifies that registers don't require a @samp{%} prefix.
 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
 
 @cindex @samp{-madd-bnd-prefix} option, i386
diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi
index ca253de..ee86dae 100644
--- a/gas/doc/c-m32r.texi
+++ b/gas/doc/c-m32r.texi
@@ -24,7 +24,7 @@
 @cindex options, M32R
 @cindex M32R options
 
-The Renease M32R version of @code{@value{AS}} has a few machine
+The Renesas M32R version of @code{@value{AS}} has a few machine
 dependent options:
 
 @table @code
@@ -72,7 +72,7 @@ data.
 
 @item -EB
 @cindex @code{-EB} option, M32R
-This is a synonum for @emph{-big}.
+This is a synonym for @emph{-big}.
 
 @item -KPIC
 @cindex @code{-KPIC} option, M32R
@@ -178,7 +178,7 @@ This is a shorter synonym for the @emph{-no-warn-unmatched-high} option.
 @cindex directives, M32R
 @cindex M32R directives
 
-The Renease M32R version of @code{@value{AS}} has a few architecture
+The Renesas M32R version of @code{@value{AS}} has a few architecture
 specific directives:
 
 @table @code
@@ -341,7 +341,7 @@ executed in parallel.
 
 @item Instructions share the same execution pipeline
 This message is produced when the assembler encounters a parallel
-instruction whoes components both use the same execution pipeline.
+instruction whose components both use the same execution pipeline.
 
 @item Instructions write to the same destination register.
 This message is produced when the assembler encounters a parallel
diff --git a/gas/doc/c-m68k.texi b/gas/doc/c-m68k.texi
index bf5ba71..470b5ad 100644
--- a/gas/doc/c-m68k.texi
+++ b/gas/doc/c-m68k.texi
@@ -454,7 +454,7 @@ the same architecture and extension set.
 
 @cindex @code{cpu} directive, M680x0
 @item .cpu @var{name}
-Select the target cpu.  Valid valuse
+Select the target cpu.  Valid values
 for @var{name} are the same as for the @option{-mcpu} command line
 option.  This directive cannot be specified after
 any instructions have been assembled.  If it is given multiple times,
diff --git a/gas/doc/c-mmix.texi b/gas/doc/c-mmix.texi
index 66a9557..6a085d8 100644
--- a/gas/doc/c-mmix.texi
+++ b/gas/doc/c-mmix.texi
@@ -79,7 +79,7 @@ is specified, and assembly fails otherwise, when an instruction needs to
 be expanded.  It needs to be kept in mind that @code{mmixal} is both an
 assembler and linker, while @code{@value{AS}} will expand instructions
 that at link stage can be contracted.  (Though linker relaxation isn't yet
-implemented in @code{@value{LD}}.)  The option @samp{-x} also imples
+implemented in @code{@value{LD}}.)  The option @samp{-x} also implies
 @samp{--linker-allocated-gregs}.
 
 @cindex @samp{--no-pushj-stubs} command line option, MMIX
diff --git a/gas/doc/c-msp430.texi b/gas/doc/c-msp430.texi
index 8630515..eb0e757 100644
--- a/gas/doc/c-msp430.texi
+++ b/gas/doc/c-msp430.texi
@@ -93,7 +93,7 @@ default behaviour.
 
 @item -my
 tells the assembler to generate a warning message if a NOP does not
-immediately forllow an instruction that enables or disables
+immediately follow an instruction that enables or disables
 interrupts.  This is the default.
 
 Note that this option can be stacked with the @option{-mn} option so
diff --git a/gas/doc/c-nds32.texi b/gas/doc/c-nds32.texi
index f40fd37..0880ae2 100644
--- a/gas/doc/c-nds32.texi
+++ b/gas/doc/c-nds32.texi
@@ -17,7 +17,7 @@
 The NDS32 processors family includes high-performance and low-power 32-bit
 processors for high-end to low-end.  @sc{gnu} @code{@value{AS}} for NDS32
 architectures supports NDS32 ISA version 3.  For detail about NDS32
-instruction set, please see the AndeStar ISA User Manual which is availible
+instruction set, please see the AndeStar ISA User Manual which is available
 at http://www.andestech.com/en/index/index.htm
 
 @menu
diff --git a/gas/doc/c-ns32k.texi b/gas/doc/c-ns32k.texi
index 1986c6a..214928d 100644
--- a/gas/doc/c-ns32k.texi
+++ b/gas/doc/c-ns32k.texi
@@ -9,7 +9,7 @@
 
 @section Options
 The 32x32 version of @code{@value{AS}} accepts a @samp{-m32032} option to
-specify thiat it is compiling for a 32032 processor, or a
+specify that it is compiling for a 32032 processor, or a
 @samp{-m32532} to specify that it is compiling for a 32532 option.
 The default (if neither is specified) is chosen when the assembler
 is compiled.
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 0fa1b58..8915db4 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -21,7 +21,7 @@
 @node RISC-V-Opts
 @section Options
 
-The following table lists all availiable RISC-V specific options
+The following table lists all available RISC-V specific options
 
 @c man begin OPTIONS
 @table @gcctabopt
diff --git a/gas/doc/c-rx.texi b/gas/doc/c-rx.texi
index 8eb6d78..b1aa97a 100644
--- a/gas/doc/c-rx.texi
+++ b/gas/doc/c-rx.texi
@@ -25,7 +25,7 @@
 @cindex options, RX
 @cindex RX options
 
-The Renesas RX port of @code{@value{AS}} has a few target specfic
+The Renesas RX port of @code{@value{AS}} has a few target specific
 command line options:
 
 @table @code
diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi
index 0e042f6..1ecdcf8 100644
--- a/gas/doc/c-s390.texi
+++ b/gas/doc/c-s390.texi
@@ -224,7 +224,7 @@ of the instruction:
 @end display
 
 There are many exceptions to the scheme outlined in the above lists, in
-particular for the priviledged instructions. For non-priviledged
+particular for the privileged instructions. For non-privileged
 instruction it works quite well, for example the instruction @samp{clgfr}
 c: compare instruction, l: unsigned operands, g: 64-bit operands,
 f: 32- to 64-bit extension, r: register operands. The instruction compares
@@ -286,7 +286,7 @@ register Xn called the index register, general register Bn called the
 base register and the displacement field Dn.
 @item Dn(Ln,Bn)
 the address for operand number n is formed from the content of general
-regiser Bn called the base register and the displacement field Dn.
+register Bn called the base register and the displacement field Dn.
 The length of the operand n is specified by the field Ln.
 @end table
 
@@ -889,7 +889,7 @@ push} saves the currently selected cpu, which may be restored with
 into double quotes in case it contains characters not appropriate
 for identifiers.  So you have to write @code{"z9-109"} instead of
 just @code{z9-109}.  Extensions can be specified after the cpu
-name, separated by plus charaters.  Valid extensions are:
+name, separated by plus characters.  Valid extensions are:
 @code{htm},
 @code{nohtm},
 @code{vx},
diff --git a/gas/doc/c-tic6x.texi b/gas/doc/c-tic6x.texi
index a0511c1..324f0b6 100644
--- a/gas/doc/c-tic6x.texi
+++ b/gas/doc/c-tic6x.texi
@@ -160,7 +160,7 @@ Output an exception type table reference to @var{symbol}.
 
 @cindex @code{.endp} directive, TIC6X
 @item .endp
-Marks the end of and exception table or function.  If preceeded by a
+Marks the end of and exception table or function.  If preceded by a
 @code{.handlerdata} directive then this also switched back to the previous
 text section.
 
diff --git a/gas/doc/c-tilegx.texi b/gas/doc/c-tilegx.texi
index a0bcc25..24c6fa2 100644
--- a/gas/doc/c-tilegx.texi
+++ b/gas/doc/c-tilegx.texi
@@ -314,7 +314,7 @@ also checks that the value does not overflow.
 
 @item tls_gd_call
 
-This modifier is used to tag an instrution as the ``call'' part of a
+This modifier is used to tag an instruction as the ``call'' part of a
 calling sequence for a TLS GD reference of its operand.
 
 @item tls_gd_add
diff --git a/gas/doc/c-tilepro.texi b/gas/doc/c-tilepro.texi
index ebd1aad..4d0afa8 100644
--- a/gas/doc/c-tilepro.texi
+++ b/gas/doc/c-tilepro.texi
@@ -282,7 +282,7 @@ if @code{tls_le_lo16} of the input value is negative.
 
 @item tls_gd_call
 
-This modifier is used to tag an instrution as the ``call'' part of a
+This modifier is used to tag an instruction as the ``call'' part of a
 calling sequence for a TLS GD reference of its operand.
 
 @item tls_gd_add
diff --git a/gas/doc/c-v850.texi b/gas/doc/c-v850.texi
index 31c785e..814cc60 100644
--- a/gas/doc/c-v850.texi
+++ b/gas/doc/c-v850.texi
@@ -411,7 +411,7 @@ register 6.
 @cindex @code{sdaoff} pseudo-op, V850
 @item sdaoff()
 Computes the offset of the named variable from the start of the Small
-Data Area (whoes address is held in register 4, the GP register) and
+Data Area (whose address is held in register 4, the GP register) and
 stores the result as a 16 bit signed value in the immediate operand
 field of the given instruction.  For example:
 
@@ -428,7 +428,7 @@ command line option].
 @cindex @code{tdaoff} pseudo-op, V850
 @item tdaoff()
 Computes the offset of the named variable from the start of the Tiny
-Data Area (whoes address is held in register 30, the EP register) and
+Data Area (whose address is held in register 30, the EP register) and
 stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
 operand field of the given instruction.  For example:
 
@@ -458,14 +458,14 @@ the offsets are signed).
 @cindex @code{ctoff} pseudo-op, V850
 @item ctoff()
 Computes the offset of the named variable from the start of the Call
-Table Area (whoes address is helg in system register 20, the CTBP
+Table Area (whose address is held in system register 20, the CTBP
 register) and stores the result a 6 or 16 bit unsigned value in the
 immediate field of then given instruction or piece of data.  For
 example:
 
      @samp{callt ctoff(table_func1)}
 
-will put the call the function whoes address is held in the call table
+will put the call the function whose address is held in the call table
 at the location labeled 'table_func1'.
 
 @cindex @code{longcall} pseudo-op, V850
diff --git a/gas/doc/c-xgate.texi b/gas/doc/c-xgate.texi
index ba15bb1..0347105 100644
--- a/gas/doc/c-xgate.texi
+++ b/gas/doc/c-xgate.texi
@@ -147,7 +147,7 @@ The register can be either @samp{R0}, @samp{R1}, @samp{R2}, @samp{R3},
 
 @end table
 
-Convience macro opcodes to deal with 16-bit values have been added.
+Convene macro opcodes to deal with 16-bit values have been added.
 
 @table @dfn
 
diff --git a/gas/doc/c-xtensa.texi b/gas/doc/c-xtensa.texi
index c2a212d..83ce837 100644
--- a/gas/doc/c-xtensa.texi
+++ b/gas/doc/c-xtensa.texi
@@ -499,7 +499,7 @@ or to:
 @end group
 @end smallexample
 
-The Xtensa assempler uses trampolines with jump around only when it cannot
+The Xtensa assembler uses trampolines with jump around only when it cannot
 find suitable unreachable trampoline.  There may be multiple trampolines
 between the jump instruction and its target.