RX: gas - Add RXv3 instruction support.

Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf

	* config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.
	(rx_bfield): Add prototype.
	(rx_post): Likewise.
	* config/rx-parse.y: Add v3 instructions and Double FPU registers.
	(DSIZE): Define.
	(POST): Define.
	(rx_check_v3): New. check v3 type.
	(rx_check_dfpu): New. check have double support.
	(double_condition_table): New. dcmp<cond> contiditon.
	(check_condition): Multiple condition support.
	(rx_lex): RXv3 instructions support.
	Add parse dcmp<cond> instruction and Double FPU registers.
	(immediate): Disable optimize in dmov #imm case.
	(displacement): Add double displacement in dmov instraction.
	* config/tc-rx.c (rx_use_conventional_section_names):
	Invert default value in rx-*-linux target.
	(cpu_type): Add additional ELF flags.
	(cpu_type_list): Add RXv3.
	(md_parse_option): Refer elf_flags from cpu_type_list.
	(md_show_usage): Add rxv3 and rxv3-dfpu.
	(rx_bytesT): Add post byte.
	(rx_bfield): New. generate bfmov / bfmovz "imm" field.
	(rx_post): New. Set instruction post byte.
	(md_assemble): Add post byte.
	doc/c-rx.texi: Add cpu types.
	* testsuite/gas/rx/Xtod.d: New.
	* testsuite/gas/rx/Xtod.sm: New.
	* testsuite/gas/rx/bfmov.d: New.
	* testsuite/gas/rx/bfmov.sm: New.
	* testsuite/gas/rx/dabs.d: New.
	* testsuite/gas/rx/dabs.sm: New.
	* testsuite/gas/rx/dadd.d: New.
	* testsuite/gas/rx/dadd.sm: New.
	* testsuite/gas/rx/dcmp.d: New.
	* testsuite/gas/rx/dcmp.sm: New.
	* testsuite/gas/rx/ddiv.d: New.
	* testsuite/gas/rx/ddiv.sm: New.
	* testsuite/gas/rx/dmov.d: New.
	* testsuite/gas/rx/dmov.sm: New.
	* testsuite/gas/rx/dmul.d: New.
	* testsuite/gas/rx/dmul.sm: New.
	* testsuite/gas/rx/dneg.d: New.
	* testsuite/gas/rx/dneg.sm: New.
	* testsuite/gas/rx/dpopm.d: New.
	* testsuite/gas/rx/dpopm.sm: New.
	* testsuite/gas/rx/dpushm.d: New.
	* testsuite/gas/rx/dpushm.sm: New.
	* testsuite/gas/rx/dround.d: New.
	* testsuite/gas/rx/dround.sm: New.
	* testsuite/gas/rx/dsqrt.d: New.
	* testsuite/gas/rx/dsqrt.sm: New.
	* testsuite/gas/rx/dsub.d: New.
	* testsuite/gas/rx/dsub.sm: New.
	* testsuite/gas/rx/dtoX.d: New.
	* testsuite/gas/rx/dtoX.sm: New.
	* testsuite/gas/rx/macros.inc: Add double FPU registers.
	* testsuite/gas/rx/mvfdc.d: New.
	* testsuite/gas/rx/mvfdc.sm: New.
	* testsuite/gas/rx/mvfdr.d: New.
	* testsuite/gas/rx/mvfdr.sm: New.
	* testsuite/gas/rx/mvtdc.d: New.
	* testsuite/gas/rx/mvtdc.sm: New.
	* testsuite/gas/rx/rstr.d: New.
	* testsuite/gas/rx/rstr.sm: New.
	* testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.
	* testsuite/gas/rx/save.d: New.
	* testsuite/gas/rx/save.sm: New.
	* testsuite/gas/rx/xor.d: New.
	* testsuite/gas/rx/xor.sm: Add pattern.

1 files changed, 4 insertions, 4 deletions

diff --git a/gas/doc/c-rx.texi b/gas/doc/c-rx.texi
index d671d09..06be2ac 100644
--- a/gas/doc/c-rx.texi
+++ b/gas/doc/c-rx.texi
@@ -108,10 +108,10 @@ alignments.  This option is the default.
 @cindex @samp{-mcpu=}
 @item -mcpu=@var{name}
 This option tells the assembler the target CPU type.  Currently the
-@code{rx100}, @code{rx200}, @code{rx600}, @code{rx610} and @code{rxv2}
-are recognised as valid cpu names.  Attempting to assemble an instruction
-not supported by the indicated cpu type will result in an error message
-being generated.
+@code{rx100}, @code{rx200}, @code{rx600}, @code{rx610}, @code{rxv2},
+@code{rxv3} and @code{rxv3-dfpu} are recognised as valid cpu names.
+Attempting to assemble an instructionnot supported by the indicated
+cpu type will result in an error message being generated.
 
 @cindex @samp{-mno-allow-string-insns}
 @item -mno-allow-string-insns