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| author | Peter Bergner <bergner@vnet.ibm.com> | 2008-08-02 04:38:51 +0000 |
|---|---|---|
| committer | Peter Bergner <bergner@vnet.ibm.com> | 2008-08-02 04:38:51 +0000 |
| commit | 9b4e57660d385d9135549aeb8360ebfa14fb3990 (patch) | |
| tree | e508e99bbab020f78ccd3b320ca8bf30b1b95b96 /gas/doc/c-ppc.texi | |
| parent | dbe454a3b5f62a101aa4a8b290a7c63a40f8ac52 (diff) | |
| download | gdb-9b4e57660d385d9135549aeb8360ebfa14fb3990.zip gdb-9b4e57660d385d9135549aeb8360ebfa14fb3990.tar.gz gdb-9b4e57660d385d9135549aeb8360ebfa14fb3990.tar.bz2 | |
gas/
* config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags.
Handle -mvsx and -mpower7.
(md_show_usage): Document -mpower7 and -mvsx.
* doc/as.texinfo (Target PowerPC): Document -mvsx.
* doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7.
gas/testsuite/
* gas/ppc/power7.d: New.
* gas/ppc/power7.s: Likewise.
* gas/ppc/ppc.exp: Run power7 test.
include/opcode/
* ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
opcodes/
* ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
(print_insn_powerpc): Prepend 'vs' when printing VSX registers.
(print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
* ppc-opc.c (insert_xt6): New static function.
(extract_xt6): Likewise.
(insert_xa6): Likewise.
(extract_xa6: Likewise.
(insert_xb6): Likewise.
(extract_xb6): Likewise.
(insert_xb6s): Likewise.
(extract_xb6s): Likewise.
(XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
XX3DM_MASK, PPCVSX): New.
(powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
"stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
Diffstat (limited to 'gas/doc/c-ppc.texi')
| -rw-r--r-- | gas/doc/c-ppc.texi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi index c71ace9..bc65685 100644 --- a/gas/doc/c-ppc.texi +++ b/gas/doc/c-ppc.texi @@ -82,6 +82,9 @@ Generate code for PowerPC e300 family. @item -maltivec Generate code for processors with AltiVec instructions. +@item -mvsx +Generate code for processors with Vector-Scalar (VSX) instructions. + @item -mpower4 Generate code for Power4 architecture. @@ -91,6 +94,9 @@ Generate code for Power5 architecture. @item -mpower6 Generate code for Power6 architecture. +@item -mpower7 +Generate code for Power7 architecture. + @item -mcell Generate code for Cell Broadband Engine architecture. |