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| author | Andrew Haley <aph@redhat.com> | 2000-02-22 18:55:30 +0000 |
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| committer | Andrew Haley <aph@redhat.com> | 2000-02-22 18:55:30 +0000 |
| commit | 6349b5f4900c4ab462bdf205da066467d4f852c2 (patch) | |
| tree | ebe534cb8d93aa83a47bbc1fe6bdf1b5e458cf66 /gas/doc/c-mips.texi | |
| parent | 50c9bd316dea4c2a2103d5856a9a942c999e16ae (diff) | |
| download | gdb-6349b5f4900c4ab462bdf205da066467d4f852c2.zip gdb-6349b5f4900c4ab462bdf205da066467d4f852c2.tar.gz gdb-6349b5f4900c4ab462bdf205da066467d4f852c2.tar.bz2 | |
2000-02-22 Andrew Haley <aph@cygnus.com>
* doc/c-mips.texi (MIPS Opts): Document -mgp32 and -mgp64.
Diffstat (limited to 'gas/doc/c-mips.texi')
| -rw-r--r-- | gas/doc/c-mips.texi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index fc2555a..6234b0c 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -67,6 +67,19 @@ Generate code for a particular MIPS Instruction Set Architecture level. @sc{r10000} processors. You can also switch instruction sets during the assembly; see @ref{MIPS ISA,, Directives to override the ISA level}. +@item -mgp32 +Assume that 32-bit general purpose registers are available. This +affects synthetic instructions such as @code{move}, which will assemble +to a 32-bit or a 64-bit instruction depending on this flag. On some +MIPS variants there is be a 32-bit mode flag; when this flag is set, +64-bit instructions generate a trap. Also, some 32-bit OSes only save +the 32-bit registers on a context switch, so it is essential never to +use the 64-bit registers. + +@item -mgp64 +Assume that 64-bit general purpose registers are available. This is +provided in the interests of symmetry with -gp32. + @item -mips16 @itemx -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting |