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| author | Jim Wilson <jimw@sifive.com> | 2023-06-01 12:10:16 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-06-01 12:25:08 +0800 |
| commit | ec2260af61501798d00e41c3180c63d25b11439c (patch) | |
| tree | 7ffe0055a6556d67d4b974e41c37205626268f39 /gas/config | |
| parent | 20ef84ed2abb990da08d90e1c978f96d29f40606 (diff) | |
| download | gdb-ec2260af61501798d00e41c3180c63d25b11439c.zip gdb-ec2260af61501798d00e41c3180c63d25b11439c.tar.gz gdb-ec2260af61501798d00e41c3180c63d25b11439c.tar.bz2 | |
RISC-V: PR30449, Add lga assembler macro support.
Originally discussion, https://github.com/riscv/riscv-isa-manual/pull/539
Added new load address pseudo instruction which is always expanded to GOT
access, no matter the .option rvc is set or not.
gas/
PR 30449
* config/tc-riscv.c (macro): Add M_LGA support.
* testsuite/gas/riscv/la-variants.d: New.
* testsuite/gas/riscv/la-variants.s: New.
include/
PR 30449
* opcode/riscv.h (M_LGA): New.
opcodes/
PR 30449
* riscv-opc.c (riscv_opcodes): Add lga support.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-riscv.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index fceb53e..7684fa7 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2010,16 +2010,20 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, case M_LA: case M_LLA: + case M_LGA: /* Load the address of a symbol into a register. */ if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) as_bad (_("offset too large")); if (imm_expr->X_op == O_constant) load_const (rd, imm_expr); - else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol. */ + /* Global PIC symbol. */ + else if ((riscv_opts.pic && mask == M_LA) + || mask == M_LGA) pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - else /* Local PIC symbol, or any non-PIC symbol. */ + /* Local PIC symbol, or any non-PIC symbol. */ + else pcrel_load (rd, rd, imm_expr, "addi", BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); break; |